Semiconductor device with vertical gate and method for fabricating the same
AssigneeHynix Semiconductor Inc.
InventorSeiichi ARITOME
Life of this patent
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Abstract
A vertical channel type non-volatile memory device having a plurality of memory cells stacked along a channel includes the channel configured to be protruded from a substrate, a tunnel insulation layer configured to surround the channel, a plurality of floating gate electrodes and a plurality of control gate electrodes configured to be alternately stacked along the channel, and a charge blocking layer interposed between the plurality of the floating gate electrodes and the plurality of the control gate electrodes alternately stacked.
Claims19
A vertical channel type non-volatile memory device having a plurality of memory cells stacked along a channel, comprising:
- the channel configured to be protruded from a substrate;
- a tunnel insulation layer configured to surround the channel;
- a plurality of floating gate electrodes and a plurality of control gate electrodes configured to be alternately stacked along the channel;
- and
- a charge blocking layer interposed between the plurality of the floating gate electrodes and the plurality of the control gate electrodes, wherein the plurality of the floating gate electrodes are alternately stacked with the plurality of the control gate electrodes.
A method for fabricating a vertical channel type non-volatile memory device, comprising:
- alternately forming a plurality of interlayer dielectric layers and a plurality of sacrificial layers over a substrate;
- forming trenches by etching the plurality of the interlayer dielectric layers and the plurality of the sacrificial layers;
- recessing the plurality of the interlayer dielectric layers exposed through an internal wall of the trenches by a predetermined depth to form recess regions;
- forming floating gate electrodes by filling the recess regions with a conductive layer;
- forming a channel by filling the trenches with a layer for a channel;
- removing the plurality of the sacrificial layers;
- forming a charge blocking layer surrounding the floating gate electrodes exposed due to the removal of the plurality of the sacrificial layers;
- and
- forming control gate electrodes adjacent to upper and lower portions of each floating gate electrode by filling a conductive layer in opened regions around the charge blocking layer.
A method for fabricating a vertical channel type non-volatile memory device, comprising:
- alternately forming a plurality of interlayer dielectric layers and a plurality of conductive layers for a control gate electrode over a substrate;
- forming trenches to expose a surface of the substrate by etching the plurality of the interlayer dielectric layers and the plurality of the conductive layers for a control gate electrode;
- recessing the plurality of the interlayer dielectric layers exposed through an internal wall of the trenches by a predetermined depth to thereby form recess regions;
- forming a charge blocking layer over the resultant structure with the recess regions;
- forming floating gate electrodes adjacent to upper and lower portions of a control gate electrode by filling a conductive layer in opened regions around the charge blocking layer;
- and
- forming a channel by filling the trenches with a layer for a channel.
Dependencies are inferred from the claim text.