Semiconductor memory, system, and method of controlling semiconductor memory

A system comprising:

• a semiconductor memory;
• and
• a controller configured to control the semiconductor memory,
• wherein the semiconductor memory includes:
• a non-volatile memory cell configured to include a floating gate and a memory transistor;
• a state machine configured to generate a normal program signal to perform a normal program operation and a verify signal to perform a verify operation in a write operation and to generate a soft program signal to perform a soft program operation when detecting a fail in the verify operation after the normal program operation, whether a threshold voltage of the memory transistor reaches a certain value in the normal program operation being checked in the verify operation;
• a voltage generating circuit configured to generate a normal program voltage and a verify voltage in response to the normal program signal and the verify signal respectively, and to generate a soft program voltage being lower than the normal program voltage in response to the soft program signal;
• and
• a determination circuit configured to detect a pass when the threshold voltage reaches the certain value and detects the fail when the threshold voltage does not reach the certain value in the verify operation.

A method of controlling a semiconductor memory, the method comprising:

• generating, in a write operation for a non-volatile memory cell including a floating gate and a memory transistor, a normal program signal for performing a normal program operation and a verify signal for performing a verify operation, whether a threshold voltage of the memory transistor reaches a certain value in the normal program operation being checked in the verify operation;
• generating a soft program signal for performing a soft program operation when detecting a fail in the verify operation after the normal program operation;
• generating a normal program voltage and a verify voltage in response to the normal program signal and the verify signal, respectively, as a control gate voltage of the memory transistor;
• generating a soft program voltage being lower than the normal program voltage in response to the soft program signal, as the control gate voltage;
• and
• detecting a pass when the threshold voltage reaches the certain value and detecting the fail when the threshold voltage does not reach the certain value in the verify operation.