N-channel sonos non-volatile memory for embedded in logic
AssigneeChip Memory Technology, Inc.
InventorsGANG-FENG FANG, Wingyu Leung
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Abstract
A system and method of an electrically programmable and erasable non-volatile memory cell fabricated using a single-poly, logic process with the addition of ONO deposition and etching is disclosed. In one embodiment, a non-volatile memory system includes at least one non-volatile memory cell consists of a SONOS transistor fabricated on a P substrate, with a deep N-well located in the P substrate, with a P-well located in the deep N-well. The memory cell further includes an access NMOS transistor, coupled to the SONOS transistor and located in the same P-well that includes an oxide only gate-dielectric. The cell can be fabricated in a modified logic process with other transistors and with their physical characteristics preserved.
Claims29
A non-volatile memory cell embedded in common logic, the cell comprising:
- an n-doped layer of silicon;
- a P-well disposed on the n-doped layer;
- and
- an NMOS transistor with an Oxide-Nitride-Oxide (ONO) gate dielectric disposed in the P-well, wherein the NMOS transistor comprises;
- a source;
- a drain;
- a channel region disposed between the source and the drain;
- and
- a poly-silicon or metal control gate disposed on the ONO gate dielectric resulting in a SONOS or a MONOS transistor, respectively.
A non-volatile memory cell prepared by a logic process comprising:
- creating an n-doped layer in a silicon substrate;
- creating a p-well in the n-doped layer;
- creating an NMOS transistor in the p-well, wherein the NMOS transistor includes a source and a drain on either side of a channel region;
- and
- creating an Oxide-Nitride-Oxide (ONO) gate dielectric overlying the P-well.
A method of fabricating a non-volatile memory (NVM) cell, the method comprising:
- creating an N-well in a P-type silicon substrate;
- creating a P-well in the N-well;
- creating an NMOS transistor in the P-well, wherein the NMOS transistor includes a source and a drain on either side of a channel region;
- and
- creating an Oxide-Nitride-Oxide (ONO) gate dielectric overlying the P-well.
An integrated circuit comprising:
- logic components having gates;
- non-volatile memory cells coupled to the logic components, wherein the non-volatile memory cells have gates;
- and
- wherein the gates of the logic components and the gates of the non-volatile memory cells each have a common single-layer poly-silicon or metal gate structure.
A method of fabricating an integrated circuit having common logic and non-volatile memory (NVM), the method comprising:
- creating an n-doped layer in a silicon substrate;
- creating a p-well in the n-doped layer;
- creating a source and a drain region for transistors in both the common logic and the non-volatile memory using a common logic process;
- and
- creating an Oxide-Nitride-Oxide (ONO) gate dielectric for non-volatile memory using a single additional gate-dielectric mask.
Dependencies are inferred from the claim text.