Multi-dot flash memory

A multi-dot flash memory comprising:

• active areas arranged by being aligned in a first direction and extending in a second direction intersecting the first direction;
• source/drain layers arranged at ends in the second direction of the active areas;
• floating gates on the active areas via a gate insulating film and arrayed in the first and second directions;
• word lines on the floating gates via an inter-electrode insulating film and extending in the first direction;
• and
• bit lines arranged by being aligned in the first direction, extending in the second direction, and arranged between the floating gates via a tunnel insulating film, wherein
• the bit lines and the floating gates are arranged alternately in the first direction.

A multi-dot flash memory comprising:

• memory cell arrays stacked on a semiconductor substrate;
• a peripheral circuit formed in the semiconductor substrate;
• and
• a memory cell array switching circuit formed in the semiconductor substrate to electrically connect a memory cell array selected from the memory cell arrays to the peripheral circuit, wherein
• each of the memory cell arrays includes:
• active areas arranged by being aligned in a first direction and extending in a second direction intersecting the first direction;
• source/drain layers arranged at ends in the second direction of the active areas;
• floating gates on the active areas via a gate insulating film and arranged in the first and second directions like an array;
• word lines on the floating gates via an inter-electrode insulating film and extending in the first direction;
• and
• bit lines arranged by being aligned in the first direction, extending in the second direction, and arranged between the floating gates via a tunnel insulating film, and
• the bit lines and the floating gates are arranged alternately in the first direction.

A method of manufacturing a multi-dot flash memory, comprising:

• forming a first insulating film on a semiconductor substrate;
• forming a first amorphous silicon film on the first insulating film;
• making a first silicon film by allowing solid phase epitaxial growth of the first amorphous silicon film in a lateral direction and crystallizing the first amorphous silicon film;
• forming a second insulating film on the first silicon film;
• forming a second amorphous silicon film on the second insulating film;
• making a second silicon film by allowing solid phase epitaxial growth of the second amorphous silicon film in the lateral direction and crystallizing the second amorphous silicon film;
• patterning the second silicon film to form second silicon films in a line & space structure extending in a first direction;
• filling a space between the second silicon films with a third insulating film;
• patterning the second silicon films, the third insulating film, the second insulating film, and the first silicon film;
• forming the first silicon film into active areas in a line & space structure extending in a second direction intersecting the first direction;
• making the second silicon films and floating gates;
• oxidizing a side along the second direction of the active areas and the floating gates;
• forming a fourth insulating film between the active areas;
• forming bit lines between the floating gates;
• forming an inter-electrode insulating film on the floating gates and the bit lines;
• and
• forming word lines extending in the first direction on the inter-electrode insulating film.