Methods of erase verification for a flash memory device

A method of performing erase verification, the method comprising:

• providing a flash memory device comprising a memory block comprising a plurality of data lines, a plurality of access lines, and a plurality of memory cells, each of the memory cells comprising a floating gate transistor comprising a control gate, each of the control gates of the floating gate transistors being electrically coupled to a respective one of the access lines;
• applying a first voltage to a selected access line of the memory block, the first voltage being substantially equal to a threshold voltage of the floating gate transistor of an erased memory cell;
• applying a second voltage to the other access lines of the memory block while the first voltage is applied to the selected access line to substantially fully turn on the floating gate transistors of the memory cells coupled to the other access lines, the second voltage being higher than the first voltage, wherein the first voltage and the second voltage are applied at least over an overlapping interval;
• detecting a current flowing from at least one of the memory cells coupled to the one of the access lines for the erase verification of the at least one memory cell;
• applying a third voltage to the selected access line of the memory block if the at least one memory cell fails the erase verification, the third voltage being higher than the first voltage and lower than the second voltage, wherein the third voltage and the second voltage are applied at least over an overlapping interval;
• and
• determining whether at least one of the memory cells coupled to the one of the access lines is turned on by the third voltage.

An apparatus comprising:

• a flash memory array comprising a plurality of memory blocks, each of the memory blocks comprising:
• a plurality of data lines;
• a plurality of access lines;
• and
• a plurality of memory cells of the data lines, each of the memory cells being electrically coupled to a respective one of the access lines;
• and
• a block erase circuit responsive to a block erase command, the block erase circuit being configured to erase all the memory cells of a selected memory block,
• wherein the block erase circuit is further configured to perform erase verification comprising determining whether the individual memory cells coupled to at least one of the data lines have been erased,
• wherein the block erase circuit is further configured to identify access lines of the memory block having a predetermined number or more of unerased memory cells, and
• wherein the block erase circuit is further configured to perform a re-erase operation only on the memory cells coupled to the identified access lines.