Method of reading data in semiconductor memory device with charge accumulation layer
AssigneeKabushiki Kaisha Toshiba
InventorToruo TAKAGIWA
Life of this patent
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Abstract
According to one embodiment, a method of reading data in a semiconductor memory device including a plurality of memory cells associated with rows and columns and a plurality of latch circuits associated with the columns includes reading flag data from the memory cells associated with one of the columns into associated one of the latch circuits, selecting one of the latch circuits sequentially, while shifting one of the latch circuits to be selected, and reading the flag data from one of the latch circuits selected in an Nth one of the shifts. N is an integer not less than 0).
Claims17
A method of reading data in a semiconductor memory device including a plurality of memory cells associated with rows and columns and a plurality of latch circuits associated with the columns, the method comprising:
- reading flag data from the memory cells associated with one of the columns into associated one of the latch circuits;
- selecting one of the latch circuits sequentially, while shifting one of the latch circuits to be selected;
- and
- reading the flag data from one of the latch circuits selected in an Nth one of the shifts (N being an integer not less than 0).
A method of reading data in a semiconductor memory device where data is capable of being read en bloc from a plurality of memory cells capable of holding 2-bit or more data according to a threshold level, the method comprising:
- reading the data en bloc from the memory cells by use of a first voltage level to determine whether data with the highest threshold level in the 2-bit or more data is present or absent;
- and
- determining according to the number of memory cells having data with the highest threshold level whether data from each of the memory cells, when the data is read en block, is 2-bit or more data or 1-bit data.
Dependencies are inferred from the claim text.