US 2011/0032751 A1Published application

Semiconductor device

AssigneeRenesas Electronics Corporation

InventorsKiyotada FUNANE, Yuta Yanagitani, Shinji Tanaka

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Abstract

The present invention is directed to provide a semiconductor device having a dual-port memory circuit in which influence of placement of replica cells exerted on enlargement of chip area is reduced. A memory cell array of a dual-port memory circuit has: a first replica cell array used to respond to an instruction of reading operation from one of dual ports; and a second replica cell array used to respond to an instruction of reading operation from the other dual port. Each of the replica cell arrays has: replica bit lines obtained by mutually short-circuiting parallel lines having a length obtained by cutting, in half, an inversion bit line and a non-inversion bit line of complementary bit lines to which data input/output terminals of a memory cell are coupled; and replica cells coupled to the replica bit lines and having transistor placement equivalent to that of the memory cells.

Claims12

Dependent claims

A semiconductor device having a dual-port memory circuit,

wherein the dual-port memory circuit comprises:
a memory cell array;
first peripheral circuits forming an access port;
and
second peripheral circuits forming another access port,
wherein the memory cell array includes:
first complementary bit lines and first word lines coupled to the first peripheral circuits;
second complementary bit lines and second word lines coupled to the second peripheral circuits;
a plurality of memory cells coupled to the first complementary bit lines, the first word lines, the second complementary bit lines, and the second word lines;
a first replica bit line and a first replica word line coupled to the first peripheral circuits;
a second replica bit line and a second replica word line coupled to the second peripheral circuits;
a plurality of replica cells having transistor placement equivalent to transistor placement of the memory cells and coupled to the first replica bit line and the first replica word line;
and
a plurality of replica cells having transistor placement equivalent to transistor placement of the memory cells and coupled to the second replica bit line and the second replica word line,
wherein the first replica bit line has a wiring structure that parallel lines having length obtained by cutting an inversion bit line and a non-inversion bit line of the first complementary bit lines in half are mutually short-circuited, and
wherein the second replica bit line has a wiring structure that parallel lines having length obtained by cutting an inversion bit line and a non-inversion bit line of the second complementary bit lines in half are mutually short-circuited.

13 more elements

Dependencies are inferred from the claim text.