NAND Based Resistive Sense Memory Cell Architecture

A solid-state data storage device, comprising:

• a base substrate of semiconductor material in which spaced-apart, localized first and second doped regions are formed;
• a gate structure supported above the base substrate spanning the first and second doped regions to form a switching device;
• first and second vertical conductive support structures that extend upwardly from the respective first and second doped regions;
• first and second horizontal conductive contact structures respectively supported by the first and second vertical conductive support structures;
• first and second resistive sense elements respectively supported on the first and second horizontal conductive contact structures;
• a third conductive support structure that extends upwardly from the first horizontal conductive contact structure;
• and
• a third horizontal conductive contact structure that interconnects the third conductive support structure with the second resistive sense element to form a tortuous path from the first resistive sense element to the second resistive sense element.