Variable resistance memory devices and methods of programming variable resistance memory devices

A variable resistance memory device, comprising:

• a variable resistance memory cell array comprising a plurality of variable resistance memory cells electrically connected between a plurality of bit lines and a plurality of words lines;
• a current limiting circuit which limits a cell current magnitude of the variable resistance memory cells;
• a by-pass circuit configured to electrically by-pass a programming pulse supplied to the variable resistance memory cells after a resistive state of the variable resistance memory cells has changed in response to the programming pulse.

A computing system comprising:

• a bus system;
• a central processing unit (CPU) operative coupled to the bus system;
• a non-volatile random access memory comprising non-volatile variable resistance memory cells, and a by-pass circuit configured to electrically by-pass a programming pulse supplied to the variable resistance memory cells after a resistive state of the variable resistance memory cells has changed in response to the programming pulse.