Semiconductor memory device
AssigneeNEC Corporation
InventorKoichi Takeda
Life of this patent
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Abstract
The SRAM cell is formed by an inverter circuit (P1, N1) using a storage node V2 as an input and a storage node V1 as an output, a load transistor P2 connected between a power source VDD and the storage node V2 using the storage node V1 as an input and the storage node V2 as an output, an access transistor N3 connected between a read bit line RBL and the storage node V1, and an access transistor N4 connected between a write bit line WBL and the storage node V2. When the access transistor N4 is controlled by a write word line WWL, the access transistor N4 can be used as holding control means and writing means for the memory cell, making it possible to obtain a semiconductor device capable of operating at a high speed with a small number of elements.
Claims25
A semiconductor device having a sense amplifier, characterized in that:
- said sense amplifier comprises:
- a read bit line and a write bit line for performing data transmission to a memory cell;
- a data line for performing data transmission to an input-output circuit;
- an inverter circuit using said read bit line as an input;
- data reading means for transmitting an output of said inverter circuit to said data line;
- first data writing means for transmitting data from said data line to said read bit line using a write enable signal;
- and
- second data writing means for transmitting inverse data of data from said data line to said write bit line using an inverse write enable signal.
A semiconductor device having a sense amplifier, characterized in that:
- said sense amplifier comprises:
- a read bit line for performing data transmission to a memory cell;
- a data line for performing data transmission to an input-output circuit;
- an inverter circuit using said read bit line as an input;
- reading means for transmitting an output of said inverter circuit to said data line;
- and
- data writing means for transmitting data from said data line to said read bit line using a write enable signal.
A semiconductor memory device characterized by comprising:
- a read word line;
- a write word line;
- and
- a sub-word driver operable to select said read word line using a main word signal and an inverse read block signal and select said write word line using said main word signal and an inverse write block signal.
A method of holding data in a semiconductor memory device having a memory cell, characterized in that said memory cell comprises an inverter circuit using a second storage node as an input and a first storage node as an output, a load transistor connected between a power source and said second storage node using said first storage node as an input, and holding control means connected to said second storage node;
- said holding control means is connected between said second storage node and a write bit line and formed by an access transistor using a write word line as a gate input;
- and data stored in said memory cell are held by setting an off-state current of said access transistor to be larger than an off-state current of said load transistor and smaller than an on-state current of said load transistor when a first low level is supplied to said write word line.
A method of reading from a semiconductor memory device having a memory cell, characterized in that said memory cell comprises an inverter circuit using a second storage node as an input and a first storage node as an output, a load transistor connected between a power source and said second storage node using said first storage node as an input, and an access transistor connected between said first storage node and a read bit line;
- and said access transistor is brought into conduction by a read word line to read data stored on said first storage node.
A method of writing to a semiconductor memory device having a memory cell, characterized in that said memory cell comprises an inverter circuit using a second storage node as an input and a first storage node as an output, a load transistor connected between a power source and said second storage node using said first storage node as an input, a first access transistor connected between said second storage node and a write bit line, and a second access transistor connected between said first storage node and a read bit line;
- said first access transistor is brought into conduction by a write word line to write from said write bit line into said second storage node;
- and said second access transistor is brought into conduction by a read word line to write from said read bit line into said first storage node.
A method of writing to a semiconductor memory device having a memory cell, characterized in that said memory cell comprises an inverter circuit using a second storage node as an input and a first storage node as an output, a load transistor connected between a power source and said second storage node using said first storage node as an input, a first access transistor connected between said second storage node and a ground potential, and a second access transistor connected between said first storage node and a read bit line;
- said first access transistor is brought into conduction by a write word line of a one-shot pulse to reset said second storage node into a low level;
- and said second access transistor is brought into conduction by a read word line to write from said read bit line into said first storage node.
A semiconductor memory device having a memory cell, characterized in that:
- said memory cell comprises:
- an inverter circuit having a first storage node and a second storage node, said inverter circuit using said second storage node as an input and said first storage node as an output;
- a load transistor connected between a power source and said second storage node, said load transistor using said first storage node as an input;
- holding control means connected to said second storage node;
- and
- one access transistor connected between a read bit line and said first storage node, wherein
- the memory cell consists of five transistors,
- said holding control means is formed by a different access transistor controlled by a write word line, and said different access transistor holds a level of said second storage node when the write word line has a first low level,
- said different access transistor is connected to said second storage node and a write bit line, said one access transistor uses a read word line as an input, data on said first storage node are read in a reading cycle by said one access transistor, and data are written into said memory cell via said one access transistor and said different access transistor in a writing cycle, and
- the semiconductor memory device further comprising a sense amplifier having another inverter circuit using said read bit line as an input, data reading means for transmitting an output of said another inverter circuit to a data line, first data writing means for transmitting data from said data line to said read bit line using a write enable signal, and second data writing means for transmitting inverse data of data from said data line to said read bit line using an inverse write enable signal.
A semiconductor memory device having a memory cell, characterized in that:
- said memory cell comprises:
- an inverter circuit having a first storage node and a second storage node, said inverter circuit using said second storage node as an input and said first storage node as an output;
- a load transistor connected between a power source and said second storage node, said load transistor using said first storage node as an input;
- holding control means connected to said second storage node;
- and
- one access transistor connected between a read bit line and said first storage node, wherein
- the memory cell consists of five transistors,
- said holding control means is formed by a different access transistor controlled by a write word line, and said different access transistor holds a level of said second storage node when the write word line has a first low level,
- said different access transistor is connected to said second storage node and a ground potential, said one access transistor uses a read word line as an input, data on said first storage node are read in a reading cycle by said one access transistor, and data from said one access transistor are written into said first storage node while said different access transistor resets said second storage node at a low level to perform a data writing operation in a writing cycle, and
- the semiconductor memory device further comprising a sense amplifier having another inverter circuit using said read bit line as an input, reading means for transmitting an output of said another inverter circuit to a data line, and data writing means for transmitting data from said data line to said read bit line using a write enable signal.
Dependencies are inferred from the claim text.