Universal three phase controllers for power converters

A control core within a three-phase controller configured to implement a control key equation to produce plurality of drive signals for a two or three-level converter, wherein two vector voltage signals, vp and vn, and two current signals, ip and in, are selected for each operating region;

• the ip and in signals are input to a signal adjustment unit;
• the voltage signals vp and vn are input to multipliers, where they are multiplied by Vm to form scalable voltage signals (Vp*Vm and Vn*Vm);
• the scalable voltage signals are then input into a second signal adjustment unit;
• the outputs of the two signal adjustment units are combined by adders (subtractors);
• the signal from the adders (subtractors) are compensated by compensator Gc(s);
• the compensated signals are compared with a sawtooth or triangular signal in order to produce leading-edge, trailing edge, or double edge pulse width modulation (PWM) drive signals Qp and Qn.

A control core includes an analog, digital, FPGA, microprocessor, and/or microcontroller circuitry configured to implement a control key equation to produce leading edge, trailing edge, or double edge PWM modulation signals to control a three-phase two-level power converter, wherein the control key equation is:

• V
• m
• ·
• [
• 1
• -
• d
• p
• 1
• -
• d
• n
• ]
• =
• [
• 2
• 1
• 1
• 2
• ]
• ·
• [
• R
• s
• ·
• i
• p
• R
• s
• ·
• i
• n
• ]
• -
• G
• e
• ·
• 
• j
• ·
• θ
• ·
• [
• 2
• 1
• 1
• 2
• ]
• ·
• [
• v
• p
• v
• n
• ]
• wherein:
• Ge is the gain value, θ is the phase offset value,
• Vm is the output signal of the voltage loop compensator,
• dp and dn are the duty ratio drive signals from the control core,
• ip and in are the selected line current signals from the signal selection unit,
• Rs is the sensing resistance for the line current signals,
• vp and vn are the selected voltage signals from the signal selection unit, and
• p and n are valued a and c, b and c, b and a, c and a, c and b, or a and b respectively depending on the region.

A control core includes an analog, digital, FPGA, microprocessor, and/or microcontroller circuitry configured to implement a control key equation to produce leading edge, trailing edge, or double edge PWM modulation signals to control a three-phase three-level power converter, wherein the control key equation is:

• V
• m
• ·
• [
• 1
• -
• d
• p
• 1
• -
• d
• n
• ]
• =
• [
• 2
• -
• 1
• -
• 1
• 2
• ]
• ·
• [
• R
• s
• ·
• i
• p
• R
• s
• ·
• i
• n
• ]
• -
• G
• e
• ·
• 
• j
• ·
• θ
• ·
• [
• 2
• -
• 1
• -
• 1
• 2
• ]
• ·
• [
• v
• p
• v
• n
• ]
• wherein:
• Ge is the gain value, θ is the phase offset value,
• Vm is the output signal of the voltage loop compensator,
• dp and dn are the duty ratio drive signals from the control core,
• ip and in are the selected line current signals from the signal selection unit,
• Rs is the sensing resistance for the line current signals,
• vp and vn are the selected voltage signals from the signal selection unit, and
• p and n are valued a and c, b and c, b and a, c and a, c and b, or a and b respectively depending on the region.

A control core includes an analog, digital, FPGA, microprocessor, and/or microcontroller circuitry configured to implement a control key equation to produce leading edge, trailing edge, or double edge PWM modulation signals to control a three-phase three-level power converter, wherein the control key equation is:

• V
• m
• ·
• [
• 1
• -
• 2
• ·
• d
• p
• 1
• -
• 2
• ·
• d
• n
• ]
• =
• [
• 2
• -
• 1
• -
• 1
• 2
• ]
• ·
• [
• R
• s
• ·
• i
• p
• R
• s
• ·
• i
• n
• ]
• -
• G
• e
• ·
• 
• j
• ·
• θ
• ·
• [
• 2
• -
• 1
• -
• 1
• 2
• ]
• ·
• [
• v
• p
• v
• n
• ]
• wherein:
• Ge is the gain value, θ is the phase offset value,
• Vm is the output signal of the voltage loop compensator,
• dp and dn are the duty ratio drive signals from the control core,
• ip and in are the selected line current signals from the signal selection unit,
• Rs is the sensing resistance for the line current signals,
• vp and vn are the selected voltage signals from the signal selection unit, and
• p and n are valued a and c, b and c, b and a, c and a, c and b, or a and b respectively depending on the region.

A control core includes an analog, digital, FPGA, microprocessor, and/or microcontroller circuitry configured to implement a control key equation to produce leading edge, trailing edge, or double edge PWM modulation signals to control a three-phase three-level power converter, wherein the control key equation is:

• V
• m
• ·
• [
• 1
• -
• d
• p
• /
• 2
• 1
• -
• d
• n
• ]
• =
• 1
• 2
• ·
• [
• 2
• 1
• 1
• 2
• ]
• ·
• [
• R
• s
• ·
• i
• p
• R
• s
• ·
• i
• n
• ]
• -
• G
• e
• ·
• 
• j
• ·
• θ
• 2
• ·
• [
• 2
• 1
• 1
• 2
• ]
• ·
• [
• v
• p
• v
• n
• ]
• wherein:
• Ge is the gain value, θ is the phase offset value,
• Vm is the output signal of the voltage loop compensator,
• dp and dn are the duty ratio drive signals from the control core,
• ip and in are the selected line current signals from the signal selection unit,
• Rs is the sensing resistance for the line current signals,
• vp and vn are the selected voltage signals from the signal selection unit, and
• p and n are valued a and c, b and c, b and a, c and a, c and b, or a and b respectively depending on the region.

A three-phase universal controller, comprising;

• a reference signal source unit integrated with a one-cycle control (OCC) controller and configured to inject reference signal into the OCC controller, the OCC controller comprising;
• a control core configured to generate a plurality of pulse width modulated (PWM) duty-ratio drive signals;
• a voltage loop compensator coupled with the control core and configured to take a taking reference voltage Vref and DC voltage feedback signal proportional to an output DC voltage Vo of a three-phase power converter and provide an output Vm coupled to the control core;
• a region selection unit configured to detect a first, second and third time-varying line voltage signals, each line voltage signal having a different phase, and configured to determine a region of operation based on zero crossings of all three time-varying voltage signals;
• a signal selection unit coupled with the region selection unit and the control core and configured to select two or more line current signals flowing through the first, second and third time varying line voltage sources and the reference signal and based on the region of operation and provide the selected signals to the control core;
• and
• a drive signal distribution unit coupled to the control core and the region selection unit, the drive signal distribution unit configured to distribute the PWM duty ratio drive signals from the control core to switches of a three-phase converter to realize non grid-tied inverters, static voltage-ampere-reactive (VAR) compensators (SVC), or power converters with the capability of any combination of a power factor corrected rectifier, a grid-tied inverter, a non-grid-tied inverter, a SVC, and an active power filter.