Reduction in kickback effect in comparators
AssigneeSTMicroelectronics Pvt. Ltd.
InventorsPratap Singh, Chandrajit Debnath
Life of this patent
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Abstract
The present disclosure relates to reduction in the effect of kickback in comparators by means of charge injection implemented by means of voltage controlled switches with attributes similar to those of an input differential pair. The voltage controlled switches produce charge to neutralize the charge loss during latching of inputs in the comparator.
Claims15
A system comprising a comparator, said system comprising:—
- a first voltage controlled unit coupled to an input voltage controlled switch;
- and
- a second voltage controlled unit coupled to a reference voltage controlled switch.
An analog to digital converter comprising a comparator, said analog to digital converter comprising:—
- a first voltage controlled unit coupled to an input voltage controlled switch;
- and
- a second voltage controlled unit coupled to a reference voltage controlled switch.
A method for reduction of kickback in a comparator comprising:
- latching inputs of the comparator to provide an output when clock signal driving the comparator goes low, thereby producing a charge across input voltage controlled switch and reference voltage controlled switch of said comparator;
- and
- producing equivalent charge across first voltage controlled unit and second voltage controlled unit of said comparator thereby neutralizing the charge produced in the latching inputs step.
A comparator comprising:
- a first transistor having a current path coupled between a source of supply voltage and an intermediate node, and a gate;
- a second transistor having a current path between the intermediate node and a first output node, and a gate forming a first input node;
- a third transistor having a current path between the intermediate node and a second output node, and a gate forming a second input node;
- a first capacitor coupled between the gate of the first transistor and the second transistor;
- and
- a second capacitor coupled between the gate of the first transistor and the third transistor.
Dependencies are inferred from the claim text.