Wide spectrum radio transmit architecture
AssigneeHarris Corporation
InventorKenneth Beghini
Life of this patent
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Abstract
A communications device (100) includes a frequency divider circuit (106) having a plurality of frequency division ratios. The device also includes at least one phase-lock loop (PLL) circuit (101, 102, 103, 104, 110, 112) coupled to at least a signal input of the frequency divider circuit. The PLL circuit includes a local oscillator (LO) circuit (104) including a plurality of voltage controlled oscillators (VCOs) having different frequency tuning ranges. The device further includes at least one control input (105) coupled to at least the frequency divider circuit and the PLL circuit for specifying one of the plurality of VCOs and one of the plurality of frequency division ratios of the frequency divider circuit.
Claims20
A communications device, comprising:
- a frequency divider circuit having a plurality of frequency division ratios;
- at least one phase-lock loop (PLL) circuit coupled to at least a signal input of said frequency divider circuit, said PLL circuit comprising a local oscillator (LO) circuit, said LO circuit comprising a plurality of voltage controlled oscillators (VCOs) having different frequency tuning ranges;
- and
- at least one control input coupled to at least said frequency divider circuit and said PLL circuit for selecting one of said plurality of VCOs and one of said plurality of frequency division ratios.
A communications device, comprising:
- a modulator for modulating a signal based on a synthesizer signal;
- and
- a frequency synthesizer for providing said synthesizer signal, said synthesizer comprising:
- a frequency divider circuit having an a plurality of frequency division ratios,
- at least one phase-lock loop (PLL) circuit coupled to at least a signal input of said frequency divider circuit, said PLL circuit comprising a local oscillator (LO) circuit comprising a plurality of voltage controlled oscillators (VCOs) having different frequency tuning ranges, and
- at least one control input coupled to at least said frequency divider circuit and said PLL circuit for selecting one of said plurality of VCOs and one of said plurality of frequency division ratios for generating said synthesizer signal.
A method of transmitting a signal using a frequency synthesizer comprising a phase-locked loop (PLL) circuit having a plurality of voltage controlled oscillators (VCOs) and a frequency divider circuit having a plurality of frequency division ratios, the method comprising:
- receiving an input reference signal for said PLL circuit and one or more control signals;
- generating at least one error signal in said PLL circuit based on at least said input reference signal and a feedback signal;
- producing an oscillator signal by coupling one of said plurality of VCOs to said frequency divider circuit based on said control signals and driving said one of said VCOs with said error signal;
- frequency dividing said oscillator signal with said frequency divider circuit by selecting one of said plurality of frequency division ratios based on said control signal;
- and
- generating said feedback signal based on said oscillator signal.
Dependencies are inferred from the claim text.