In-rush/out-rush current limiting circuit and devices containing same
AssigneeATI Technologies ULC
InventorHusein Afaneh
Life of this patent
Estimating the term…
Abstract
An in-rush or out-rush current limiting circuit employs a low number of components to effect in-rush current limiting and may be employed in dongles or on-chip (in the case of serving as an out-rush current limiting circuit). The in-rush current limiting circuit may be employed, for example, in USB dongles, Display Port (DP) dongles, or any other suitable connector as desired. Alternatively, the circuit may be integrated onto a circuit board or within an integrated circuit as desired. Among other advantages, a lower cost, low complexity solution may be provided. In addition, bulk capacitance can be increased such as by employing a trickle resistor or other suitable limiting structure.
Claims9
An in-rush current limiting circuit comprising:
- a PMOS transistor having a gate, source and drain, the source operative to receive a supply voltage from an external voltage supply source, the drain operative to provide an internal supply voltage based on the external supply voltage;
- a capacitor having a first node coupled to the source and a second node;
- and
- a resistor having a third node coupled to the second node of the capacitor and the PMOS gate and a fourth node coupled to receive a ground potential.
A portable universal serial communication bus (USB) device comprising:
- a male USB connector operative to provide an external supply voltage for internal circuitry of the portable USB device;
- an in-rush current limiting circuit comprising:
- a PMOS transistor having a gate, source and drain, the source operative to receive the external supply voltage, the drain operative to provide an internal supply voltage for the internal circuitry based on the external supply voltage;
- a capacitor having a first node coupled to the source and a second node;
- a resistor having a third node coupled to the second node of the capacitor and the PMOS gate and a fourth node coupled to receive a ground potential;
- an internal voltage regulator operatively coupled to receive the internal supply voltage from the in-rush current limiting circuit and to provide one or more regulated supply voltages;
- and
- internal circuitry operatively coupled to receive the one or more regulated supply voltages from the voltage regulator.
An out-rush current limiting circuit comprising:
- a PMOS transistor having a gate source and drain, the source operative to receive an internal supply voltage, the drain operative to provide an external supply voltage based on the internal supply voltage;
- a transistor having an input operatively coupled to the drain of the PMOS transistor;
- an output operatively coupled to the gate of the PMOS transistor;
- a trickle resistor operatively coupled across the source and drain of the PMOS transistor;
- and
- a voltage divider operatively coupled across the PMOS transistor.
A portable connector comprising:
- a connector;
- a PMOS transistor, operatively coupled to the connector, having a gate source and drain, the source operative to receive an internal supply voltage, the drain operative to provide an external supply voltage based on the internal supply voltage;
- a transistor having an input operatively coupled to the drain of the PMOS transistor and an output operatively coupled to the gate of the PMOS transistor;
- a trickle resistor operatively coupled across the source and drain of the PMOS transistor;
- and
- a voltage divider operatively coupled across the PMOS transistor.
An apparatus comprising:
- a hot plug transistor operatively responsive to a hot plug signal from a remote connector;
- and
- an out-rush current limiting circuit operative to limit out rush current during a hot plug condition, the circuit comprising:
- a PMOS transistor having a gate source and drain, the source operative to receive an internal supply voltage, the drain operative to provide an external supply voltage based on the internal supply voltage;
- a transistor having an input operatively coupled to the drain of the PMOS transistor;
- an output operatively coupled to the gate of the PMOS transistor;
- a trickle resistor operatively coupled across the source and drain of the PMOS transistor;
- and
- a voltage divider operatively coupled across the PMOS transistor.
A computer readable medium comprising:
- executable instructions stored therein that when executed by an integrated circuit design system cause the integrated circuit design system to design an integrated circuit comprising:
- an out-rush current limiting circuit comprising:
- a PMOS transistor having a gate source and drain, the source operative to receive an internal supply voltage, the drain operative to provide an external supply voltage based on the internal supply voltage;
- a transistor having an input operatively coupled to the drain of the PMOS transistor and an output operatively coupled to the gate of the PMOS transistor;
- a trickle resistor operatively coupled across the source and drain of the PMOS transistor;
- and
- a voltage divider operatively coupled across the PMOS transistor.
Dependencies are inferred from the claim text.