US 2011/0032013 A1 · Digital Phase-Locked Loop Clock System

Abstract

A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock and a second input for a feedback signal, and outputting a difference signal representing a phase and/or frequency difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for accumulating the difference signal over time. The sigma-delta modulator (SDM) may have a control input coupled to the buffer. The adder may have inputs coupled to the (SDM) and a source of an integer control word. The first frequency divider may have an input for a clock signal and a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the input clock signal divided by (N+F/M), wherein N is determined by the integer control word and F/M is determined by an output of the SDM. The system clock also may include a phase-locked loop (PLL) including a phase/frequency detector that has a first input coupled to the output of the DCO and a second input that is phase-locked to the first input, and a second frequency divider coupled from the second input of the PLL to the second input of the DPFD.

Claims18

Dependent claims

A clock system, comprising:

a first phase/frequency detector (PFD) having a first input for a reference clock and a second input for a feedback clock, and outputting a difference signal representing a phase and/or frequency difference between the reference clock and the feedback clock;
a buffer coupled to the first PFD to store the difference signal over time;
a digitally-controlled oscillator (DCO) comprising:
a sigma-delta modulator (SDM) having a control input coupled to the buffer,
an adder having inputs coupled to the (SDM) and a source of an integer control word, and
a first frequency divider having a clock input for a source clock signal and a control input coupled to the adder, the first frequency divider generating an output clock as an output clock of the DCO having an average frequency representing a frequency of the source clock signal divided by (N+F/M), wherein N is determined by the integer control word and F/M is determined by an output of the SDM;
a phase-locked loop (PLL) including a second PFD that has a first input to receive the output clock of the DCO and a second input that is phase-locked to the first input;
and
a second frequency divider coupled from the second input of the second PFD of the PLL to the second input of the first PFD.

6 more elements

A clock system, comprising:

a digital phase/frequency detector (DPFD) having a first input for a reference clock, a second input for a feedback clock, the DPFD generating an output representing a difference between the reference clock and the feedback clock;
a buffer coupled to the DPFD for storing the difference signal over time;
a digitally-controlled oscillator (DCO) comprising
a sigma-delta modulator (SDM) having a control input coupled to the buffer,
an adder having inputs coupled to the (SDM) and a source of an integer control word, and
a first frequency divider having a clock input for a source clock signal and a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the source clock signal divided by (N+F/M), wherein N is determined by the integer control word and F/M is determined by an output of the SDM;
and
a second frequency divider coupled to the DCO output clock signal outputting the feedback clock to the DPFD.

5 more elements

Dependencies are inferred from the claim text.

Digital Phase-Locked Loop Clock System

Life of this patent

Digital Phase-Locked Loop Clock System

Life of this patent

Abstract

Claims18