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US 2011/0032012 A1Published application
Phase-locked loop circuit
AssigneeFujitsu Semiconductor Limited
InventorAkira KUMAGAI
Life of this patent
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Abstract
A phase-locked loop circuit includes a control loop including a frequency divider configured to frequency-divide an output clock and to control a frequency of the output clock according to a phase difference between a local clock and a phase-divided local clock; and a control unit configured to control a frequency dividing ratio of the frequency divider according to a phase difference between the output clock and an input clock that corresponds to data taken in based on the output clock.
Claims11
A phase-locked loop circuit comprising:
- a control loop including a frequency divider configured to frequency-divide an output clock and to control a frequency of the output clock according to a phase difference between a local clock and a phase-divided local clock;
- and
- a control unit configured to control a frequency dividing ratio of the frequency divider according to a phase difference between the output clock and an input clock that corresponds to data taken in based on the output clock.
A phase-locked loop circuit comprising:
- a first phase comparator configured to compare a phase of a local clock signal with a phase of a first clock signal and to output a signal according to a comparison result;
- a voltage-controlled oscillator configured to output an output clock signal with a frequency according to a voltage of the signal that is output from the first phase comparator;
- a first frequency divider configured to frequency-divide an output clock signal that is output from the voltage-controlled oscillator and to output the frequency-divided output signal to the first phase comparator as the first clock signal;
- a second phase comparator configured to compare a phase of an input clock signal with an output clock signal that is output from the voltage-controlled oscillator;
- and
- a control unit configured to control a phase-dividing ratio of the first frequency divider according to a signal that is output from the second phase comparator.
3 more elements
Dependencies are inferred from the claim text.