US 2011/0032009 A1 · DELAY LOCKED LOOP CIRCUIT

Abstract

A delay locked loop circuit comprising a VCDL which outputs a feedback clock by delaying an input clock in accordance with a magnitude of a control voltage, a phase comparator which detects a phase difference between the feedback clock and a reference clock by comparing the feedback clock with the reference clock, and outputs an Up-signal for raising the control voltage and a Down-signal for lowering the control voltage in accordance with the phase difference, a control voltage generation circuit which determines the control voltage in accordance with the Up-signal and the Down-signal, and outputs the control voltage to the VCDL, and a reset circuit which resets the phase comparator based on a logical OR between the reference clock and a first intermediate clock which is a signal obtained by delaying the input clock by the VCDL and is output before the feedback clock.

Claims12

Dependent claims

A delay locked loop circuit comprising:

a voltage controlled delay line (VCDL) which outputs a feedback clock by delaying an input clock in accordance with a magnitude of a control voltage;
a phase comparator which detects a phase difference between the feedback clock and a reference clock by comparing the feedback clock with the reference clock, and outputs an Up-signal for raising the control voltage and a Down-signal for lowering the control voltage in accordance with the phase difference;
a control voltage generation circuit which determines the control voltage in accordance with the Up-signal and the Down-signal, and outputs the control voltage to said voltage controlled delay line;
and
a reset circuit which resets said phase comparator based on an logical OR between the reference clock and a first intermediate clock which is a signal obtained by delaying the input clock by said voltage controlled delay line and is output before the feedback clock.

2 more elements

A delay locked loop circuit comprising:

a voltage controlled delay line (VCDL) which outputs a reference clock and a feedback clock by delaying an input clock in accordance with a magnitude of a control voltage;
a phase comparator which detects a phase difference between the reference clock and the feedback clock by comparing the feedback clock with the reference clock, and outputs an Up-signal for raising the control voltage and a Down-signal for lowering the control voltage in accordance with the phase difference;
a control voltage generation circuit which determines the control voltage in accordance with the Up-signal and the Down-signal, and outputs the control voltage to said voltage controlled delay line;
and
a reset circuit which resets said phase comparator based on an logical OR between the input clock and a first intermediate clock which is a signal obtained by delaying the input clock by said voltage controlled delay line and is output before the feedback clock.

2 more elements

Dependencies are inferred from the claim text.

Delay locked loop circuit

Life of this patent

Delay locked loop circuit

Life of this patent

Abstract

Claims12