Ultra-low power multi-threshold asynchronous circuit design
AssigneeBoard of Trustees of the University of Arkansas
InventorsJia Di, Scott Christopher Smith
Life of this patent
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Abstract
A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.
Claims25
An early completion input incomplete asynchronous circuit (ECII), the ECII comprising:
- a delay insensitive register having a data input, a data output, a request input, and an acknowledge output;
- a multi-threshold null convention logic circuit having a data input coupled to the delay insensitive register data output, a sleep input, and an output coupled to a data input of a delay insensitive register of a subsequent ECII;
- and
- an early completion circuit having a first input coupled to the acknowledge output, a second input coupled to the request input, and an output coupled to the sleep input and to a request input of a delay insensitive register of a previous ECII.
A fixed early completion input incomplete asynchronous circuit (FECII), the FECII comprising:
- a delay insensitive register having a data input, a data output, a request input, and an acknowledge output;
- a multi-threshold null convention logic circuit having a data input coupled to the delay insensitive register data output, a sleep input, and an output coupled to a data input of a delay insensitive register of a subsequent FECII;
- an early completion circuit having a first input coupled to the acknowledge output, a second input coupled to an output of an early completion circuit of a subsequent FECII, and an output coupled to the sleep input and to an input of an early completion circuit of a previous FECII;
- and
- an inverter coupled to the output of the early completion circuit and having an output coupled to the request input.
An early completion input incomplete asynchronous circuit (ECII), the circuit comprising:
- a delay insensitive register having a data input and a data output;
- a multi-threshold null convention logic circuit having a data input coupled to the delay insensitive register data output, a sleep input, and a data output;
- and
- a slept early completion circuit having a first input coupled to an output of an early completion circuit of a subsequent ECII, a second input coupled to the output of an early completion circuit of a previous ECII, a third input coupled to the delay insensitive register data input, and an output coupled to the sleep input.
A multi-threshold null convention logic circuit, the circuit comprising:
- a first circuit coupled to Vcc;
- a set circuit coupled to the first circuit;
- a first high-threshold transistor coupled between the set circuit and ground, the first high-threshold transistor driven by a SLEEP signal;
- a second high-threshold transistor coupled to Vcc and driven by a SLEEP signal;
- a first low-threshold transistor coupled to the second high-threshold transistor and driven by the coupling between the first circuit and the set circuit;
- a third high-threshold transistor coupled between the first low-threshold transistor and ground and driven by the coupling between the first circuit and the set circuit;
- a second low-threshold transistor coupled between the coupling of the third high-threshold transistor and the first low-threshold transistor and ground, the second low-threshold transistor driven by the SLEEP signal;
- and
- an output coupled to the coupling between the third high-threshold transistor, the first low-threshold transistor, and the second low-threshold transistor.
Dependencies are inferred from the claim text.