Air channel interconnects for 3-d integration

A method of forming interconnected air channels within semiconductor wafers comprising the steps of:

• processing an upper wafer to form one or more semiconductor devices and circuitry for connecting the one or more semiconductor devices in a device layer located on a front surface of the upper wafer;
• forming a plurality of air vias in a portion of the upper wafer and a plurality of through-silicon vias (TSVs) in another portion of the upper wafer;
• filling each of the plurality of air vias with a material comprising one of a conductive material or a dummy material and filling each of the plurality of TSVs with a conductive material;
• forming a protective structure on the air vias and a bonding pad on the TSVs;
• forming a stud for wafer bonding on the bonding pad located on the TSVs;
• removing at least a portion of the protective structure and the conductive material from inside the air vias, thereby forming a plurality of vertical air channels and an opening exposing the plurality of vertical air channels;
• processing a lower wafer to form one or more semiconductor devices and circuitry for connecting the one or more semiconductor devices in a device layer located on a front surface of the lower wafer;
• forming a bonding pad on the device layer located on a front surface of the lower wafer;
• depositing an insulating layer on the lower wafer, including on the bonding pad;
• forming an opening in the insulating layer exposing the bonding pad;
• aligning and bonding the upper wafer and the lower wafer to each other, thereby forming an embedded air channel interconnect network which includes the vertical air channels and a horizontal air channel which are interconnected to each other within at a bonding interface between the bonded upper wafer and lower wafer;
• thinning a backside of the upper wafer to expose the vertical air channels and the TSVs;
• and
• forming a passivation layer on the exposed surface of the backside of the upper wafer.

A semiconductor structure comprising:

• a plurality of layers bonded together, each of the layers having semiconductor devices and interconnection lines and vias, wherein the lines and the vias of at least one of the layers are electrically interconnected to the lines and the vias of at least another of the layers;
• an air channel interconnect network embedded within the semiconductor structure, wherein the air channel interconnect network is located within at least two of the layers of the plurality of layers bonded together and also in between the at least two wafers of the plurality of layers bonded together at a bonding interface thereof;
• and
• an opening located in a peripheral region of the semiconductor structure in which a gas may flow into and out of the air channel interconnect network through this opening to cool the semiconductor structure.

A method for fabricating a three-dimensional integrated (IC) chip stack structure having interconnected horizontal and vertical air channels embedded therein comprising:

• processing a plurality of wafers to have one or more IC active device strata formed therein,
• forming a plurality of vertical air channels in at least one of the plurality of wafers,
• forming an air channel opening in an upper region of at least another of the plurality of wafers;
• bonding and electrically interconnecting the plurality of wafers together such that there is an electrical connection between the IC active devices, wherein the at least one wafer having the vertical air channels formed therein is bonded to the at least another wafer having the channel opening formed in an upper surface thereof such that the vertical air channels formed within the at least one wafer are interconnected to the channel opening of the at least another wafer at a bonding interface between the at least one wafer and the at least another wafer;
• thinning the backside of at least one of the wafers;
• depositing a passivation layer on a surface of the at least one wafer;
• and
• dicing the bonded wafers to form the 3D IC chip stack structure having the interconnected horizontal and vertical air channels embedded therein.