System-in-package with fan-out wlcsp
AssigneeMediatek Inc.
InventorsNan-Cheng Chen, Chih-Tai Hsu
Life of this patent
Estimating the term…
Abstract
A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier; a second semiconductor die mounted alongside of the first semiconductor die; a rewiring laminate structure comprising a re-routed metal layer between the first semiconductor die and the package carrier. At least a portion of the re-routed metal layer projects beyond the die edge. A plurality of bumps are arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier.
Claims28
A system-in-package, comprising:
- a package carrier;
- a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face;
- a second semiconductor die mounted on the package carrier adjacent to the first semiconductor die;
- a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge;
- and
- a plurality of bumps arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier.
A system-in-package, comprising:
- a package carrier having a chip side and an opposite side;
- a fan-out wafer level device comprising a first semiconductor die mounted on the chip side of the package carrier;
- a second semiconductor die mounted on the chip side of the package carrier and adjacent to the fan-out wafer level device and
- an underfill between the package carrier and the fan-out wafer level device.
A system-in-package, comprising:
- a package carrier having a chip side and an opposite side;
- a fan-out wafer level device comprising a first semiconductor die mounted on the chip side of the package carrier;
- a second semiconductor die mounted on the chip side of the package carrier and adjacent to the fan-out wafer level device;
- and
- a molding compound encapsulating the fan-out wafer level device and the molding compound filling into a gap between the package carrier and the fan-out wafer level device.
A system-in-package, comprising:
- a package carrier having a chip side and an opposite side;
- a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to the chip side of the package carrier, wherein a plurality of contact pads are situated on the die face;
- a second semiconductor die mounted on the chip side of the package carrier and adjacent to the first semiconductor die;
- a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge;
- a plurality of bumps arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier;
- and
- a plurality of solder balls on the opposite side of the substrate.
Dependencies are inferred from the claim text.