Packaging substrate having embedded semiconductor chip

A packaging substrate having an embedded semiconductor chip, comprising:

• a core board having a first surface and an opposite second surface and a cavity penetrating the first and second surfaces;
• a semiconductor chip disposed in the cavity and having an active surface with a plurality of electrode pads and an opposite inactive surface;
• a first reinforcing dielectric layer disposed on the first surface of the core board and the active surface of the semiconductor chip and filling the gap between the semiconductor chip and the cavity, wherein the first reinforcing dielectric layer comprises a reinforcing material;
• a second reinforcing dielectric layer disposed on the second surface of the core board and the inactive surface of the semiconductor chip and filling the gap between the semiconductor chip and the cavity, wherein the second reinforcing dielectric layer comprises a reinforcing material;
• and
• first and second wiring layers disposed on the first and second reinforcing dielectric layers, respectively, and the first wiring layer electrically connecting to the electrode pads.