# US 2011/0031603 A1 · Semiconductor devices having stress relief layers and methods for fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2011/0031603 A1 - Document ID: US20110031603A1 - Status: Published application - Kind: A1 - Application number: 12/538,293 - Filed: 2009-08-10 - Published: 2011-02-10 - Earliest claimed: 2009-08-10 - Assignees: Globalfoundries Inc. - Inventors: Michael SU; Frank KUCHENMEISTER; Lei FU - Web page: https://patentgrep.com/patent/US20110031603A1 ## CPC - H10W 74/129: {forming a chip-scale package [CSP]} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 72/019: {of bond pads} - H10W 72/01255: {by using masks} - H10W 72/0198: {batch processes} - H10W 72/07227: {involving guiding structures, e.g. spacers or supporting members} - H10W 72/07231: {Techniques} - H10W 72/07236: {Soldering or alloying} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/251: {Materials} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/931: {Shapes of bond pads} - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Methods are provided for fabricating a semiconductor device. In accordance with an exemplary embodiment, a method comprises the steps of providing a semiconductor die having a conductive terminal, forming an insulating layer overlying the semiconductor die, and forming a cavity in the insulating layer which exposes the conductive terminal. The method also comprises forming a first stress-relief layer in the cavity, forming an interconnecting structure having a first end electrically coupled to the first stress-relief layer, and having a second end, and electrically and physically coupling the second end of the interconnecting structure to a packaging substrate. ## Claims ### Claim 1 A method of fabricating a semiconductor device comprising the steps of: providing a semiconductor die having a conductive terminal; forming an insulating layer overlying the semiconductor die; forming a cavity in the insulating layer which exposes the conductive terminal; forming a first stress-relief layer in the cavity; forming an interconnecting structure having a first end electrically coupled to the first stress-relief layer, and having a second end; and electrically and physically coupling the second end of the interconnecting structure to a packaging substrate. ### Claim 2 (depends on 1) The method of claim 1, further comprising the step of forming a second stress-relief layer interposed between the second end of the interconnecting structure and the packaging substrate. ### Claim 3 (depends on 2) The method of claim 2, further comprising the step of dicing the semiconductor die from a semiconductor substrate after the step of forming a first stress-relief layer. ### Claim 4 (depends on 3) The method of claim 3, wherein the step of dicing the semiconductor die is performed after the step of forming a second stress-relief layer. ### Claim 5 (depends on 1) The method of claim 1, wherein the step of forming a first stress-relief layer comprises forming a first stress-relief layer having a shear modulus less than that of substantially pure copper. ### Claim 6 (depends on 1) The method of claim 1, wherein the step of forming a first stress-relief layer comprises forming a first stress-relief layer formed of a material selected from a group consisting of Sn, Ag, In, Bi, Cu, Pb, Au, Ni, Mg, Al, and alloys thereof. ### Claim 7 (depends on 1) The method of claim 1, wherein the step of forming an interconnecting structure comprises forming a copper interconnecting structure. ### Claim 8 (depends on 1) The method of claim 1, wherein the step of forming a first stress-relief layer comprises forming a first stress-relief layer by electroplating. ### Claim 9 (depends on 1) The method of claim 1, further comprising the step of forming a patterned first stress-relief layer. ### Claim 10 (depends on 1) The method of claim 1, further comprising the step of planarizing the first stress-relief layer. ### Claim 11 (depends on 1) The method of claim 1, further comprising the step of forming a patterned organic layer on the conductive terminal before forming the first stress-relief layer. ### Claim 12 (depends on 11) The method of claim 11, wherein the step of forming a patterned organic layer is performed after the step of forming a first stress-relief layer. ### Claim 13 A method of fabricating a semiconductor device comprising the steps of: providing a semiconductor die having a first conductive terminal; providing a packaging substrate having a second conductive terminal; forming a first stress-relief layer in electrical communication with the first conductive terminal; forming an interconnecting structure having a first end coupled to the first stress-relief layer, and having a second end; forming a second stress-relief layer on the second conductive terminal; and electrically and physically coupling the second stress-relief layer to the second end of the interconnecting structure. ### Claim 14 (depends on 13) The method of claim 13, further comprising the step of forming an organic layer having an opening on the first conductive terminal. ### Claim 15 (depends on 14) The method of claim 14, wherein the step of forming a first stress-relief layer comprises forming a first stress-relief layer in the opening. ### Claim 16 (depends on 14) The method of claim 14, further comprising the step of depositing a seed layer on the first conductive terminal prior to the step of forming a first stress-relief layer and after the step of forming an organic layer. ### Claim 17 (depends on 14) The method of claim 14, wherein the step of forming an organic layer comprises forming an organic layer that circumscribes the periphery of the first conductive terminal. ### Claim 18 (depends on 14) The method of claim 14, wherein the step of forming an organic layer having an opening comprises forming an organic layer having a substantially polygon-shaped opening. ### Claim 19 (depends on 14) The method of claim 14, wherein the step of forming an organic layer having an opening comprises forming an organic layer having a substantially circular opening. ### Claim 20 An electronic device comprising: a packaging substrate; a semiconductor die having a conductive terminal; a first stress-relief layer in electrical communication with the conductive terminal; and an interconnecting structure having a first end electrically and physically coupled to the first stress-relief layer, and having a second end electrically and physically coupled to the packaging substrate.