Stacked semiconductor package
AssigneeHynix Semiconductor Inc.
InventorJae Ho Jo
Life of this patent
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Abstract
A stacked semiconductor package includes a first semiconductor package having a first semiconductor chip having a first surface and a second surface facing away from the first surface, first bonding pads disposed on the first surface, and through-electrodes electrically connected with the first bonding pads The through-electrodes pass through the first and second surfaces of the first chip and extend from the second surface. A second semiconductor package has a through-holes defined therein into which the through-electrodes are inserted and second bonding pads electrically connected with the through-electrodes.
Claims14
A stacked semiconductor package comprising:
- a first semiconductor package comprising:
- a first semiconductor chip having a first surface and a second surface facing away from the first surface comprising;
- a first bonding pad disposed on the first surface of the first semiconductor chip;
- and
- a through-electrode electrically connected with the first bonding pad, passing through the first and second surfaces, such that a portion of the through-electrode extends out of the second surface;
- and
- a second semiconductor package comprising a second semiconductor chip having a through-hole defined therein, wherein is the portion of the through-electrode that extends out of the second surface is inserted into the through-hole and electrically connected with a second bonding pad.
Dependencies are inferred from the claim text.