Gate dielectric first replacement gate processes and integrated circuits therefrom

A method for fabricating a CMOS integrated circuit (IC), comprising:

• providing a substrate having a semiconductor surface, said semiconductor surface having PMOS regions for PMOS devices and NMOS regions for NMOS devices;
• forming a gate dielectric layer on said PMOS regions and said NMOS regions, wherein said gate dielectric layer comprises a high-k dielectric material having a k-value >10;
• forming an original polysilicon comprising gate electrode layer on said gate dielectric;
• doping said original polysilicon comprising gate electrode layer in both said PMOS regions and said NMOS regions n-type to a doping level of at least 1×1018 cm−3;
• applying a gate masking layer on said original polysilicon comprising gate electrode layer;
• etching to pattern said original polysilicon comprising gate electrode layer to simultaneously form original gate electrodes for said PMOS devices and said NMOS devices;
• forming source/drain regions for said PMOS devices and said NMOS devices;
• depositing at least one pre-planarization dielectric layer;
• chemical mechanical polishing (CMP) to planarize and expose said original gate electrodes;
• removing said original gate electrodes for said PMOS devices and said NMOS devices to form trenches using a wet etch solution comprising at least one non-alkali hydroxide solution, wherein at least a portion of said high-k gate dielectric layer is preserved;
• forming metal comprising replacement gates in said trenches, and
• completing fabrication of said IC.

An integrated circuit (IC) including at least one replacement gate MOS device, said replacement gate MOS device comprising:

• a substrate having a semiconductor surface;
• a gate stack on said semiconductor surface comprising a patterned metal comprising gate electrode layer over a gate dielectric layer, wherein said patterned metal comprising gate electrode layer has a top surface and said gate dielectric has a length dimension in a source-drain direction of said MOS device;
• a gate sidewall comprising at least one dielectric layer on a sidewall of said gate stack, and
• a source and a drain on opposing sides of said gate stack;
• wherein:
• (i) a position of said top surface of said patterned metal comprising gate electrode layer and a position of a top surface of said gate sidewall proximate to said patterned metal comprising gate electrode layer are within 1 nm of one another, and
• (ii) a length of said top of said patterned metal comprising gate electrode layer is within 0.5 nm of said length dimension of said gate dielectric layer.