Fin interconnects for multigate fet circuit blocks
AssigneeInfineon Technologies AG
InventorHarald Gossner
Life of this patent
Estimating the term…
Abstract
In an embodiment, an apparatus includes a first field effect transistor including a first source contact region, a first drain contact region and a first plurality of fins overlying a substrate, a first gate overlying the first plurality of fins, the first source contact region coupled to first ends of the first plurality of fins, and a second field effect transistor including a second source contact region, a second drain contact region, and a second plurality of fins overlying the substrate, a second gate overlying the second plurality of fins, and an interconnection contact region overlying the substrate, electrically coupling the first drain contact region and the second source contact region and abutting the first and the second pluralities of fins.
Claims20
An apparatus comprising:
- a first contact region electrically coupled to first ends of a first plurality of fins;
- a second contact region electrically coupled to first ends of a second plurality of fins;
- a first gate line operatively coupled to and overlying the first plurality of fins and the second plurality of fins;
- a second gate line operatively coupled to and overlying the second plurality of fins;
- and
- an interconnect contact region electrically coupling and abutting second ends of the first plurality of fins and the second plurality of fins.
An apparatus comprising:
- a first contact region electrically coupled to a first plurality of fins and a second plurality of fins;
- a second contact region electrically coupled to a third plurality of fins and a fourth plurality of fins;
- a first gate line operatively coupled to and overlying the first plurality of fins and the second plurality of fins;
- a second gate line operatively coupled to and overlying the third plurality of fins and the fourth plurality of fins;
- a first local interconnect contact region electrically coupling and abutting the first plurality of fins and the third plurality of fins;
- and
- a second local interconnect contact region electrically coupling and abutting the second plurality of fins and the fourth plurality of fins, wherein the first contact region, the second contact region, the first plurality of fins, the second plurality of fins, the third plurality of fins and the fourth plurality of fins overlay a semiconductor substrate.
A method of fabricating a fin interconnect, comprising:
- forming a mask layer on a top surface of a substrate;
- forming a first fin pattern and a second fin pattern on the mask layer, wherein the first fin pattern and the second fin pattern include a shared region interposed between their respective adjacent edges;
- and
- forming a first plurality of fins determined by the first fin pattern and a second plurality of fins determined by the second fin pattern, wherein the first plurality of fins and the second plurality of fins include an interconnect contact region corresponding to the shared region.
Dependencies are inferred from the claim text.