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US 2011/0031554 A1Published application
Structure and method to improve threshold voltage of mosfets including a high k dielectric
AssigneeInternational Business Machines Corporation
InventorsSunfei Fang, Brian J. Greene, Effendi Leobandung, Qingqing Liang, Edward P. Maciejewski, Yanfeng Wang
Life of this patent
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Abstract
A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner is formed on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.
Claims25
A method of fabricating a semiconductor structure comprising:
- providing at least one patterned gate stack in at least one device region of a semiconductor substrate, said at least one patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor;
- and
- forming a conformal nitride-containing liner on at least exposed sidewalls of the patterned gate dielectric material, wherein said forming the conformal nitride-containing liner is performed at a temperature of less than 500° C. in a nitrogen-containing ambient.
A method of fabricating a CMOS structure comprising:
- providing a first patterned gate stack in a first device region of a semiconductor substrate, and a second patterned gate stack in a second device region of the semiconductor substrate, said first patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide, and a patterned gate conductor and said second patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide, and a patterned gate conductor;
- and
- forming a conformal nitride-containing liner on at least exposed sidewalls of the patterned gate dielectric material in both device regions, wherein said forming the conformal nitride-containing liner is performed at a temperature of less than 500° C. in a nitrogen-containing ambient.
A method of fabricating a CMOS structure comprising:
- providing a first patterned gate stack in a first device region of a semiconductor substrate, and a second patterned gate stack in a second device region of the semiconductor substrate, said first patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor and said second patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor;
- forming an embedded semiconductor material having a different lattice constant than the semiconductor substrate within the semiconductor substrate at a footprint of one of the patterned gate stacks;
- selectively exposing a sidewall of said patterned gate dielectric material of each of said patterned gate stacks;
- and
- forming a conformal nitride-containing liner on at least exposed sidewalls of the patterned gate dielectric material in both device regions, wherein said forming the conformal nitride-containing liner is performed at a temperature of less than 500° C in a nitrogen-containing ambient.
2 more elements
A semiconductor structure comprising:
- at least one patterned gate stack in at least one device region of a semiconductor substrate, said at least one patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor;
- and
- a conformal nitride-containing liner located on at least exposed sidewalls of the patterned gate dielectric material, said conformal nitride-containing liner having a thickness of from 0.5 nm to 50 nm.
A semiconductor structure comprising:
- a first patterned gate stack in a first device region of a semiconductor substrate, and a second patterned gate stack in a second device region of the semiconductor substrate, wherein said first patterned gate stack includes from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor and said second patterned gate stack includes from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor;
- and
- a conformal nitride-containing liner located on at least exposed sidewalls of the patterned gate dielectric material in both device regions, the conformal nitride-containing liner having a thickness of from 0.5 nm to 50 nm.
Dependencies are inferred from the claim text.