Method for manufacturing semiconductor device and apparatus for manufacturing same
AssigneeKabushiki Kaisha Toshiba
InventorsTsuneo UENAKA, Kazuyuki Higashi
Life of this patent
Estimating the term…
Abstract
A method for manufacturing a semiconductor device includes: forming a first layer on a substrate; forming a first contact hole in the first layer; burying a sacrificial film in the first contact hole; forming a second layer on the first layer and the first contact hole after burying; forming a second contact hole reaching the sacrificial film in the second layer; removing the sacrificial film from the first contact hole via the second contact hole; and providing a contact electrode in the first contact hole and the second contact hole.
Claims20
A method for manufacturing a semiconductor device comprising:
- forming a first layer on a substrate;
- forming a first contact hole in the first layer;
- burying a sacrificial film in the first contact hole;
- forming a second layer on the first layer and the first contact hole after burying;
- forming a second contact hole reaching the sacrificial film in the second layer;
- removing the sacrificial film from the first contact hole via the second contact hole;
- and
- providing a contact electrode in the first contact hole and the second contact hole.
A semiconductor device comprising:
- a substrate;
- a stacked body provided on the substrate and including a plurality of conductive layers and a plurality of insulating layers alternately being stacked, the stacked body including a contact hole, the contact hole including a first contact hole reaching the substrate and a second contact hole formed on the first contact hole to be connected to the first contact hole and having a smaller hole diameter than the first contact hole;
- and
- a contact electrode provided in the contact hole formed in the stacked body.
A semiconductor device comprising:
- a substrate including a memory cell array region and a peripheral circuit region formed around the memory cell array region;
- a stacked body provided on the substrate over the memory cell array region and the peripheral circuit region and including a plurality of conductive layers and a plurality of insulating layers alternately stacked;
- a semiconductor layer provided in a memory hole formed in the stacked body in the memory cell array region and aligning in a stacking direction of the conductive layers and the insulating layers;
- a charge storage layer provided between the conductive layers and the semiconductor layer;
- and
- a contact electrode provided in a contact hole formed in the stacked body in the peripheral circuit region,
- the contact hole including:
- a first contact hole reaching the substrate;
- and
- a second contact hole formed on the first contact hole to be connected to the first contact hole and having a smaller hole diameter than the first contact hole.
Dependencies are inferred from the claim text.