Two-Step STI Formation Process
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorKa-Hing Fung
Life of this patent
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Abstract
A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming a first isolation region in the semiconductor substrate; after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source/drain region; and after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate.
Claims20
An integrated circuit structure comprising:
- a semiconductor substrate comprising an active region;
- a first shallow trench isolation (STI) region contacting a first side edge of the active region;
- a gate electrode over the active region and the first STI region;
- a source/drain region adjacent the gate electrode, with a portion of the active region forming the source/drain region;
- a trench in the semiconductor substrate and contacting a second side edge of the active region;
- and
- an inter-layer dielectric (ILD) extending from over the gate electrode to inside the trench, wherein a portion of the ILD in the trench forms a second STI region.
An integrated circuit structure comprising:
- a semiconductor substrate comprising a first active region and a second active region;
- a first shallow trench isolation (STI) region in the semiconductor substrate, wherein the first STI region contacts the first and the second active regions;
- a first gate electrode strip directly over the first active region and the first STI region;
- a second gate electrode strip directly over the second active region and the first STI region, wherein the first and the second gate electrode strips are substantially parallel to each other;
- a first source/drain region in the first active region and adjacent the first gate electrode strip;
- a second source/drain region in the second active region and adjacent the second gate electrode strip;
- and
- an inter-layer dielectric (ILD) having a top surface higher than top surfaces of the first and the second gate electrode strips, wherein the ILD extends into the semiconductor substrate to form a second STI region contacting sidewalls of the first and the second source/drain regions.
An integrated circuit structure comprising:
- a semiconductor substrate comprising an active region;
- a first shallow trench isolation (STI) region in the semiconductor substrate;
- a metal-oxide-semiconductor (MOS) device comprising:
- a gate stack directly over the active region and the first STI region;
- a source/drain region adjacent the gate stack and in a portion of the active region;
- and
- a source/drain silicide region over the source/drain region;
- and
- a second STI region in the semiconductor substrate, wherein the source/drain region and the source/drain silicide region comprise first portions contacting the first STI region, and second portions contacting the second STI region, and wherein top surfaces of the second portions are flatter than top surfaces of the first
Dependencies are inferred from the claim text.