Semiconductor devices having line type active regions and methods of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorKye-Hee Yeom
Life of this patent
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Abstract
In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line type active regions are disposed over the semiconductor substrate. Here, the gate electrodes include both a device gate electrode and a recessed device isolation gate electrode. Alternatively, each of the gate electrodes is constituted of a device gate electrode and a plan type device isolation gate electrode, and a width of the plan type device isolation gate electrode greater than a width of the device gate electrode.
Claims13
A semiconductor device, comprising:
- a device isolation layer which defines line type active regions in a semiconductor substrate;
- and
- gate electrodes which are disposed over the semiconductor substrate to be parallel to each other and intersect the line type active regions,
- wherein the gate electrodes include both a device gate electrode and a plan type device isolation gate electrode, and wherein a width of the plan type device isolation gate electrode is greater than a width of the device gate electrode.
A semiconductor device fabricating method, comprising steps of:
- forming a device isolation layer which defines active regions in a semiconductor substrate, the active regions having a line type structure;
- forming channel trenches which intersect the line type active regions in the semiconductor substrate;
- forming a conformal gate insulating layer on top surfaces of the line type active regions and inner surfaces of the channel trenches;
- and
- forming recessed device gate electrodes filling the channel trenches and plan type device isolation gate electrodes which are parallel to the recessed device gate electrode on the semiconductor substrate having the gate insulating layer, wherein a width of the plan type device isolation gate electrode is formed to be greater than a width of the recessed device gate electrode.
Dependencies are inferred from the claim text.