Device with stressed channel

A circuit structure, comprising:

• at least one NFET device, said NFET device comprises an n-source and an n-drain that are each provided with an n-extension, wherein said NFET device is provided in an NFET portion at a surface of a Si substrate, wherein said n-extensions are mutually connected through an n-channel and respectively extend at said surface from said n-source and said n-drain towards said n-channel, wherein said n-source and said n-drain and said n-extensions are composed of SiC having a smaller lattice constant than said Si substrate, whereby due to said smaller lattice constant said n-source and said n-drain and said n-extensions are imparting a tensile state of stress onto said n-channel;
• and
• at least one PFET device, said PFET device comprises a p-source and a p-drain that are each provided with a p-extension, wherein said PFET device is provided in a PFET portion at said surface of said Si substrate, wherein said p-extensions are mutually connected through a p-channel and respectively extend at said surface from said p-source and said p-drain towards said p-channel, wherein said p-source and said p-drain and said p-extensions each contain Ge, whereby having a larger lattice constant than said Si substrate, and due to said larger lattice constant said p-source and said p-drain and said p-extensions are imparting a compressive state of stress onto said p-channel.

A method for fabricating an FET device, comprising:

• providing for a channel at a surface of a Si substrate, and overlapping said channel with a gate, wherein said gate has sidewalls;
• forming a first recession in said Si substrate to a first depth on opposing sides of said gate, wherein laterally said first recession reaches said channel on both said opposing sides of said gate;
• filling said first recession with a first epitaxial material;
• providing a spacer over said sidewalls;
• forming a second recession in said Si substrate to a second depth on opposing sides of said gate, wherein said second depth is greater than said first depth, wherein laterally said second recession is spaced away from said channel by said spacer on both said opposing sides of said gate;
• filling said second recession with a second epitaxial material, wherein said first and said second epitaxial materials are selected to have different lattice constants than said Si substrate, wherein a state of stress is imparted onto said channel;
• and
• wherein said second epitaxial material and said first epitaxial material are being characterized as forming a source and a drain and their respective extensions for said FET device.

A method for fabricating a circuit structure, comprising:

• defining at least one NFET portion and at least one PFET portion at a surface of a Si substrate;
• masking said at least one NFET portion;
• on said at least one PFET portion processing a PFET device such that said PFET device comprises a p-source and a p-drain that are each provided with a p-extension, wherein said p-extensions are mutually connected through a p-channel while respectively extending at said surface from said p-source and said p-drain towards said p-channel, wherein said p-source and said p-drain and said p-extensions each contain Ge, whereby having a larger lattice constant than said Si substrate, and due to said larger lattice constant said p-source and said p-drain and said p-extensions are imparting a compressive state of stress onto said p-channel;
• masking said at least one PFET portion;
• and
• on said at least one NFET portion processing an NFET device such that said NFET device comprises an n-source and an n-drain that are each provided with an n-extension, wherein said n-extensions are mutually connected through an n-channel while respectively extending at said surface from said n-source and said n-drain towards said n-channel, wherein said n-source and said n-drain and said n-extensions are composed of SiC having a smaller lattice constant than said Si substrate, whereby due to said smaller lattice constant said n-source and said n-drain and said n-extensions are imparting a tensile state of stress onto said n-channel.