Semiconductor device and manufacturing method thereof
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsShunpei YAMAZAKI, Miyuki HOSOBA, Junichiro SAKATA, Hideaki KUWABARA
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AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsShunpei YAMAZAKI, Miyuki HOSOBA, Junichiro SAKATA, Hideaki KUWABARA
Estimating the term…
An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.
A semiconductor device comprising:
A semiconductor device comprising:
A method of forming a semiconductor device, comprising the steps of:
Dependencies are inferred from the claim text.