Nanomesh SRAM Cell

A SRAM array, comprising:

• a plurality of SRAM cells formed on a wafer, each cell comprising at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on the wafer, wherein each pass gate comprises:
• one or more device layers each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the pass gate device layers are doped with at least one n-type dopant;
• a gate common to each of the pass gate device layers surrounding the nanowire channels,
• wherein each inverter comprises:
• a plurality of device layers each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the inverter device layers are doped with at least one n-type dopant and the source and drain regions of one or more other of the inverter device layers are doped with at least one p-type dopant;
• and
• a gate common to each of the inverter device layers surrounding the nanowire channels.

A method for fabricating a SRAM cell, comprising the steps of:

• forming at least one pair of pass gates by forming, for each pass gate, one or more device layers on a wafer, each pass gate device layer including a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, and forming a gate common to each of the pass gate device layers surrounding the nanowire channels;
• forming at least one pair of inverters by forming, for each inverter, a plurality of device layers adjacent to the pass gate device layers on the wafer, each inverter device layer including a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, and forming a gate common to each of the inverter device layers surrounding the nanowire channels;
• introducing at least one n-type dopant into the source and drain regions of one or more of the pass gate device layers;
• introducing at least one n-type dopant into the source and drain regions of one or more of the inverter device layers;
• and
• introducing at least one p-type dopant into the source and drain regions of one or more other of the inverter device layers.