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US 2011/0031470 A1Published application
Methods for fabricating passivated silicon nanowires and devices thus obtained
AssigneeCalifornia Institute of Technology
InventorsAxel Scherer, Sameer Walavalkar, Michael D. Henry, Andrew P. Homyk
Life of this patent
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Abstract
Methods for fabricating passivated silicon nanowires and an electronic arrangement thus obtained are described. Such arrangements may comprise a metal-oxide-semiconductor (MOS) structure such that the arrangements may be utilized for MOS field-effect transistors (MOSFETs) or opto-electronic switches.
Claims32
A method for fabricating an electronic arrangement, comprising:
- providing one or more nanoscale pillars;
- coating the one or more nanoscale pillars with an insulator;
- depositing a first conductive layer on the insulator;
- coating a portion of the first conductive layer with a dielectric;
- removing an end portion of the first conductive layer and the insulator, thereby making electrically accessible a portion of the one or more nanoscale pillars;
- and
- depositing a second conductive layer on the dielectric, the second conductive layer contacting the electrically accessible portion of the one or more nanoscale pillars.
4 more elements
A method for fabricating an electronic arrangement, comprising:
- providing one or more nanoscale pillars;
- coating the one or more nanoscale pillars with an insulator;
- coating the insulator with a dielectric;
- removing an end portion of the insulator, thereby making electrically accessible a portion of the one or more nanoscale pillars;
- and
- depositing a conductive layer on the dielectric, the conductive layer contacting the electrically accessible portion of the one or more nanoscale pillars.
3 more elements
A method for fabricating an electronic arrangement, comprising:
- providing one or more nanoscale pillars;
- coating the one or more nanoscale pillars with an insulator;
- removing the insulator portion in contact with the nanoscale pillar;
- coating remaining insulator portion and an exposed portion of the nanoscale pillar with a first conductive layer;
- coating the conductive layer with a dielectric;
- removing an end portion of the first conductive layer, thereby making electrically accessible a portion of the one or more nanoscale pillars;
- and
- depositing a second conductive layer on the dielectric, the second conductive layer contacting the electrically accessible portion of the one or more nanoscale pillars.
5 more elements
An electronic arrangement comprising:
- a plurality of insulator covered semiconductor nanoscale pillar structures substantially perpendicular to a planar surface;
- and
- a conductive layer coated on the insulator covered semiconductor nanoscale pillar structures.
An electronic arrangement comprising:
- an insulator covered semiconductor substrate;
- a plurality of nanoscale pillar structures on the substrate, substantially perpendicular to a planar surface;
- and
- a conductive layer covering the insulator and the nanoscale pillar structures, wherein the conductive layer is devoid of an end portion thereof, so that end portions of the nanoscale pillar structures are electrically accessible.
1 more element
Dependencies are inferred from the claim text.