Processor system and fault managing unit thereof
AssigneesSTMicroelectronics S.r.l., Parades S.C.A.R.L.
InventorsUmberto Macri, Alberto Ferrari, Massimo Baleani, Antonio Anastasio
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Abstract
A processor system having a processor core, a plurality of modules connected to the processor core and configured to generate respective fault signals, and a fault managing unit connected to the processor core and to the plurality of modules. The fault managing unit is adapted to collect a first fault signal generated by a first module of the plurality of modules which is in a fault condition, analyze said collected first fault signal, and generate a first reaction signal to be selectively transmitted to said processor core and said first module.
Claims23
A processor system, comprising:
- a processor core;
- a plurality of modules connected to the processor core and configured to generate respective fault signals;
- and
- a fault managing unit connected to the processor core and to the plurality of modules;
- the fault managing unit adapted to:
- collect a first fault signal generated by a first module of the plurality of modules which is in a fault condition;
- analyze said collected first fault signal;
- and
- generate a first reaction signal to be selectively transmitted to said processor core and said first module.
An electrical system, comprising
- a processor core,
- a plurality of modules connected to the processor core and configured to generate respective fault signals;
- and
- an automotive apparatus controlled by said processor core;
- and
- a fault managing unit configured so as to:
- collect a fault signal generated by one module of the plurality of modules which is in a fault condition;
- analyze said collected fault signal;
- and
- generate a reaction signal to be selectively transmitted to said processor core and said module in fault condition.
A circuit, comprising:
- an input module connectable to a core processor and to a plurality of operative modules;
- the input module configured to receive fault signals generated by the plurality of modules;
- a diagnosis and reaction module structured to analyze a first fault signal received from one of said modules that is in a fault condition and to generate a reaction signal to be selectively sent to the processor core and the module in the fault condition in accordance with a criticality data associated with the fault signal;
- an output module connected to the diagnosis and reaction module to selectively transmit the first reaction signal to the core processor and to the module in the fault condition.
Dependencies are inferred from the claim text.