Integrated Circuit Cell Library with Cell-Level Process Compensation Technique (PCT) Application and Associated Methods

A method for performing cell-level process compensation technique (PCT) processing, comprising:

• (a) selecting a cell to be PCT processed;
• (b) defining a lithographic buffer region around a level of the cell;
• (c) performing PCT processing on the level of the cell surrounded by the lithographic buffer region;
• (d) generating an as-fabricated aerial image of the PCT processed level of the cell;
• (e) measuring edge differentials between as-fabricated features in the aerial image and corresponding features in a layout of the cell level to ensure adequacy of PCT processing;
• and
• (f) upon adequate PCT processing, storing the PCT processed cell level and corresponding as-fabricated aerial image on a computer readable storage medium.

A method for analyzing a transistor, comprising:

• generating a simulated aerial image of an as-fabricated active region of a transistor;
• delineating differentiated active region areas along each side of a gate electrode of the transistor based on the simulated aerial image of the as-fabricated active region;
• virtually slicing the transistor into segments based on the delineation of differentiated active region areas along each side of the gate electrode of the transistor;
• and
• storing each transistor segment in a computer readable format suitable for processing by a circuit analysis tool.