Memory system and data transfer method
OwnerTakahide NISHIYAMAinventor
Life of this patent
Estimating the term…
Abstract
A memory system includes a nonvolatile memory configured to store data, a first buffer configured to temporarily store data from the nonvolatile memory, a correction circuit configured to correct an error of data from the first buffer, a second buffer configured to temporarily store data from the correction circuit, a bus configured to receive data from the second buffer, a command sequence unit configured to issue a command for data transfer between modules, the modules including the first buffer, the correction circuit and the second buffer, and a command decode unit configured to decode the command and to generate a control signal for controlling the data transfer.
Claims20
A memory system comprising:
- a nonvolatile memory configured to store data;
- a first buffer configured to temporarily store data from the nonvolatile memory;
- a correction circuit configured to correct an error of data from the first buffer;
- a second buffer configured to temporarily store data from the correction circuit;
- a bus configured to receive data from the second buffer;
- a command sequence unit configured to issue a command for data transfer between modules, the modules including the first buffer, the correction circuit and the second buffer;
- and
- a command decode unit configured to decode the command and to generate a control signal for controlling the data transfer.
A data transfer method of a memory system, the memory system comprising:
- a nonvolatile memory configured to store data;
- a first buffer configured to temporarily store data from the nonvolatile memory;
- a correction circuit configured to correct an error of data from the first buffer;
- a second buffer configured to temporarily store data from the correction circuit;
- and
- a bus configured to receive data from the second buffer,
- the method comprising:
- issuing a command for data transfer between modules, the modules including the first buffer, the correction circuit and the second buffer;
- and
- decoding the command and generating a control signal for controlling the data transfer.
Dependencies are inferred from the claim text.