Semiconductor integrated circuit and method of testing the same
AssigneeRenesas Electronics Corporation
InventorNaoki Kaneko
Life of this patent
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Abstract
A semiconductor integrated circuit includes: a plurality of scan flip-flops configured to form a scan chain in a scan test; and a plurality of clock gating circuits connected between a clock input and corresponding portions of the plurality of scan flip-flops, respectively. The plurality of clock gating circuits are connected in serial to form a chain and gating setting data is inputted in serial through the chain connection. Each of the plurality of clock gating circuits controls a connection between the clock input and a corresponding portion of the plurality of scan flip-flops based on the gating setting data.
Claims7
A semiconductor integrated circuit comprising:
- a plurality of scan flip-flops configured to form a scan chain in a scan test;
- and
- a plurality of clock gating circuits connected between a clock input and corresponding portions of said plurality of scan flip-flops, respectively,
- wherein said plurality of clock gating circuits are connected in serial to form a chain and gating setting data is inputted in serial through the chain connection, and
- wherein each of said plurality of clock gating circuits controls a connection between the clock input and a corresponding portion of said plurality of scan flip-flops based on said gating setting data.
A test method of a semiconductor integrated circuit, comprising:
- setting connection or disconnection of a clock input for each of portions of a plurality of scan flip-flops of a scan chain;
- and
- inputting a test pattern data to said scan chain to which the connection or the disconnection is set.
Dependencies are inferred from the claim text.