Compactor independent direct diagnosis of test hardware

One or more computer-readable media storing computer-executable instructions for causing a computer system to perform a method of testing an integrated circuit, the method comprising:

• receiving test responses from testing scan chains of a circuit-under-test using multiple chain patterns, wherein the testing comprises,
• applying at least one of the chain patterns to the scan chains through a decompressor and a compactor coupled to the scan chains, and
• applying at least one of the chain patterns to the scan chains while bypassing the decompressor and the compactor;
• and
• determining whether a fault exists in the scan chains of the circuit-under-test or in the decompressor or the compactor based at least in part on test responses to the chain patterns applied during the testing.

One or more computer-readable media comprising computer-executable instructions for causing a computer system to perform a method of testing an integrated circuit, the method comprising:

• simulating one or more test patterns being applied to an integrated circuit design having scan chains and a compactor and thereby generating one or more expected compressed test responses, the act of simulating comprising modifying test values of the test patterns so that scan cells of a selected scan chain are loaded with either unknown values or a fixed value, the act of simulating further comprising using a transformation function representative of the compactor to generate the expected compressed test responses;
• comparing the expected compressed test responses to observed compressed test responses obtained from testing a physical embodiment of the integrated circuit design with the one or more test patterns;
• and
• determining a range of suspect scan cells in the selected scan chain based at least in part on the comparison.

One or more computer-readable media storing computer-executable instructions for causing a computer system to perform a method, the method comprising:

• receiving a circuit description of an at least partially scan-based circuit-under-test and a compactor for compacting test responses captured in the circuit-under-test;
• determining a transformation function performed by the compactor to the test responses captured in the circuit-under-test;
• and
• diagnosing scan chain faults in one or more scan chains of the circuit-under-test using a diagnostic procedure that incorporates the transformation function.