Out-of-order execution microprocessor with reduced store collision load replay reduction

A method for reducing the likelihood of having to replay a load instruction in an out-of-order execution microprocessor due to a store collision, the microprocessor having a register alias table (RAT) configured to encounter instructions in program order and to generate dependencies used to determine when the instructions may execute out of program order, the method comprising:

• allocating an entry of a queue of entries, in response to replay of a load instruction on a first instance;
• populating the allocated entry to hold an instruction pointer of the load instruction and to hold information useable to identify a store instruction that caused the load instruction to be replayed on the first instance;
• determining, in response to the RAT encountering the load instruction on a second instance, that the load instruction second instance instruction pointer matches the instruction pointer of an entry of the queue;
• and
• causing the load instruction on the second instance to have a dependency on the store instruction identified by the information in the matching entry.

A computer program product for use with a computing device, the computer program product comprising:

• a computer usable storage medium, having computer readable program code embodied in said medium, for specifying an out-of-order execution microprocessor for reducing the likelihood of having to replay a load instruction due to a store collision, the computer readable program code comprising:
• first program code for specifying a queue of entries, each entry configured to hold an instruction pointer of a load instruction and to hold information useable to identify a store instruction that caused the load instruction to be replayed on a first instance of the load instruction;
• and
• second program code for specifying a register alias table (RAT), coupled to the queue of entries, the RAT configured to encounter instructions in program order and to generate dependencies used to determine when the instructions may execute out of program order, wherein the RAT is configured to encounter the load instruction on a second instance, to determine that the load instruction second instance instruction pointer matches the instruction pointer of an entry of the queue, and to cause the load instruction on the second instance to have a dependency on the store instruction identified by the information in the matching entry.