Out-of-order execution microprocessor with reduced store collision load replay reduction

A method for reducing the likelihood of having to replay a load instruction in an out-of-order execution microprocessor due to a store collision, the microprocessor having a register alias table (RAT) configured to encounter instructions in program order and to generate dependencies used to determine when the instructions may execute out of program order, the method comprising:

• allocating an entry of a first queue of entries and populating the allocated entry with an instruction pointer of a load instruction, in response to determining that the load instruction must be replayed;
• allocating an entry of a second queue of entries, when the RAT encounters a store instruction, and populating the allocated entry with a dependency that identifies an instruction upon which the store instruction depends for its data;
• and
• causing a subsequent instance of the load instruction to share the dependency that identifies the instruction upon which the store instruction of one of the second queue entries depends for its data, when the RAT encounters the subsequent instance of the load instruction and determines that its instruction pointer matches the instruction pointer of an entry of the first queue.

A computer program product for use with a computing device, the computer program product comprising:

• a computer usable storage medium, having computer readable program code embodied in said medium, for specifying a an out-of-order execution microprocessor for reducing the likelihood of having to replay a load instruction due to a store collision, the computer readable program code comprising:
• first program code for specifying a first queue of entries;
• second program code for specifying a second queue of entries;
• and
• third program code for specifying a register alias table (RAT), coupled to the first and second queues of entries, the RAT configured to encounter instructions in program order and to generate dependencies used to determine when the instructions may execute out of program order, the RAT further configured to:
• allocate an entry of the first queue and populate the allocated entry with an instruction pointer of a load instruction, when the RAT determines that the load instruction must be replayed;
• allocate an entry of the second queue, when the RAT encounters a store instruction, and populate the allocated entry with a dependency that identifies an instruction upon which the store instruction depends for its data;
• and
• cause a subsequent instance of the load instruction to share the dependency that identifies the instruction upon which the store instruction of one of the second queue entries depends for its data, when the RAT encounters the subsequent instance of the load instruction and determines that its instruction pointer matches the instruction pointer of an entry of the first queue.