Guaranteed prefetch instruction

A microprocessor, comprising:

• a cache memory;
• microcode, configured to implement an architectural repeat string move instruction, the microcode including a series of guaranteed prefetch-load-store instruction triplets;
• and
• a memory subsystem, configured to execute the guaranteed prefetch, load, and store instructions and to prefetch into the cache memory cache lines specified by the guaranteed prefetch instructions even in the presence of a predetermined set of conditions in the presence of which the memory subsystem only treats non-guaranteed prefetch instructions as a hint.

A microprocessor, comprising:

• a cache memory;
• microcode, configured to implement an architectural repeat string move instruction, the microcode including a plurality of load and store instructions to move the string from a source memory location to a destination memory location, the microcode further including a plurality of prefetch instructions sufficiently preceding the plurality of load instructions to increase the likelihood of cache lines being present in the cache memory prior to their access by the plurality of load instructions;
• and
• a memory subsystem, configured to execute the prefetch, load, and store instructions, wherein the memory subsystem is configured to detect a condition that one of the plurality of prefetch instructions is specifying a memory address that misses in a translation lookaside buffer (TLB) of the microprocessor and to responsively cause the microcode to be notified of the TLB miss.

A method to be performed by a microprocessor having a cache memory and an instruction set having first and second prefetch instructions, the method comprising:

• detecting the presence of one or more of a predetermined set of conditions while executing an instance of the first prefetch instruction, wherein the first prefetch instruction instructs the microprocessor to prefetch a first cache line of data from a system memory into the cache memory;
• foregoing prefetching the first cache line of data from the system memory into the cache memory, in response to said detecting the presence of one or more of a predetermined set of conditions while executing an instance of the first prefetch instruction;
• detecting the presence of one or more of the predetermined set of conditions while executing an instance of the second prefetch instruction, wherein the second prefetch instruction instructs the microprocessor to prefetch a second cache line of data from the system memory into the cache memory;
• and
• completing prefetching the second cache line of data from the system memory into the cache memory, in response to said detecting the presence of one or more of the predetermined set of conditions while executing the instance of the second prefetch instruction.

A method to be performed by a microprocessor having a cache memory and microcode, the method comprising:

• decoding an architectural repeat string move instruction;
• executing a plurality of load and store instructions to move the string from a source memory location to a destination memory location, in response to said decoding the architectural repeat string move instruction;
• executing a plurality of prefetch instructions sufficiently prior to said executing the plurality of load instructions to increase the likelihood of cache lines being present in the cache memory prior to their access by the plurality of load instructions, wherein the plurality of load and store instructions and the plurality of prefetch instructions are instructions of the microcode of the microprocessor;
• and
• detecting a condition that one of the plurality of prefetch instructions is specifying a memory address that misses in a translation lookaside buffer (TLB) of the microprocessor and responsively causing the microcode to be notified of the TLB miss.