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US 2010/0306489 A1Published application
Error management firewall in a multiprocessor computer
AssigneeCray Inc.
InventorsDennis C. Abts, Steven L. Scott, Aaron F. Godfrey
Life of this patent
Estimating the term…
Abstract
A multiprocessor computer system comprises a plurality of processors and a plurality of nodes, each node comprising one or more processors. A local memory in each of the plurality of nodes is coupled to the processors in each node, and a hardware firewall comprising a part of one or more of the nodes is operable to prevent a write from an unauthorized processor from writing to the local memory.
Claims18
A multiprocessor computer system, comprising:
- a plurality of processors;
- a plurality of nodes, each node comprising one or more processors;
- a local memory in each of the plurality of nodes, the memory coupled to the processors in each node;
- and
- a hardware firewall comprising a part of one or more of the nodes, the firewall operable to prevent a write from an unauthorized processor from writing to the local memory.
2 more elements
A method of preventing errors in a multiprocessor computer system, comprising:
- a hardware firewall comprising a part of one or more nodes in the multiprocessor computer, each node comprising one or more processors, the firewall operable to prevent a write from an unauthorized processor from writing to a local memory in the node.
A computer processing node, comprising:
- one or more local processors;
- a connection to one or more other processing nodes;
- a local memory coupled to the one or more local processors;
- and
- a hardware firewall operable to prevent a write from an unauthorized processor from writing to the local memory.
2 more elements
Dependencies are inferred from the claim text.