Data cache with modified bit array
AssigneeVIA Technologies, Inc.
InventorsRodney E. Hooker, Colin Eddy, G. Glenn Henry
Life of this patent
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AssigneeVIA Technologies, Inc.
InventorsRodney E. Hooker, Colin Eddy, G. Glenn Henry
Estimating the term…
A cache memory system includes a first array of storage elements each configured to store a cache line, a second array of storage elements corresponding to the first array of storage elements each configured to store a first partial status of the cache line in the corresponding storage element of the first array, and a third array of storage elements corresponding to the first array of storage elements each configured to store a second partial status of the cache line in the corresponding storage element of the first array. The second partial status indicates whether or not the cache line has been modified. When the cache memory system modifies the cache line within a storage element of the first array, it writes only the second partial status in the corresponding storage element of the third array to indicate that the cache line has been modified but refrains from writing the first partial status in the corresponding storage element of the second array. The cache memory system reads both the first partial status and the second partial status to determine the full status.
A cache memory system, comprising:
A method for accessing a cache memory system, the method comprising:
A computer program product for use with a computing device, the computer program product comprising:
Dependencies are inferred from the claim text.