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US 2010/0306474 A1Published application
Cache line use history based done bit modification to i-cache replacement scheme
AssigneeInternational Business Machines Corporation
InventorDavid A. Luick
Life of this patent
Estimating the term…
Abstract
A method of providing history based done logic for instructions includes receiving an instruction in a cache line in a L2 cache; and loading the cache line into an L1 cache with a history count that indicates the number of read references of the previous access.
Claims17
A method of providing history based done logic for instructions, the method comprising:
- receiving an instruction in a cache line in a L2 cache;
- and
- loading the cache line into an L1 cache with a history count that indicates the number of read references of the previous access.
An integrated circuit device, comprising:
- a processor core;
- a level one cache;
- a level two cache;
- and
- a history count in the level one cache for indicating a number of read references to an instruction in a cache line a last time the cache line was called in to the level one cache.
2 more elements
A processor device, comprising:
- a level one cache;
- a level two cache;
- circuitry configured to:
- receive an instruction in a cache line in a L2 cache and loading the cache line into an L1 cache with a history count that indicates the number of read references of the previous access.
1 more element
Dependencies are inferred from the claim text.