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US 2010/0306473 A1Published application
Cache line use history based done bit modification to d-cache replacement scheme
AssigneeInternational Business Machines Corporation
InventorDavid A. Luick
Life of this patent
Estimating the term…
Abstract
A method of providing history based done logic includes receiving a cache line in a L2 cache; determining if the cache line has a history of access at least three times on a previous call into the L2 cache; providing the cache line directly to a processor if the history of access was less then the at least three times; and loading the cache line into an L1 cache if the history of access was the at least three times.
Claims18
A method of providing history based done logic, the method comprising:
- receiving a cache line in a L2 cache;
- determining if the cache line has a history of access at least three times on a previous call into the L2 cache;
- providing the cache line directly to a processor if the history of access was less then the at least three times;
- and
- loading the cache line into an L1 cache if the history of access was the at least three times.
2 more elements
An integrated circuit device, comprising:
- a processor core;
- a level one cache;
- a level two cache;
- and
- a history count in the level one cache for indicating a number of load references to the cache line a last time the cache line was called in to the level one cache.
2 more elements
A processor device, comprising:
- a level one cache;
- a level two cache;
- and
- circuitry configured to:
- receive a cache line in a L2 cache;
- determine if the cache line has a history of access at least three times on a previous call into the L2 cache;
- provide the cache line directly to a processor if the history of access was less then the at least three times;
- and load the cache line into an L1 cache if the history of access was the at least three times.
5 more elements
Dependencies are inferred from the claim text.