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US 2010/0306471 A1Published application
D-cache line use history based done bit based on successful prefetchable counter
AssigneeInternational Business Machines Corporation
InventorDavid A. Luick
Life of this patent
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Abstract
A method of providing history based done logic for a D-cache includes receiving a D-cache line in an L2 cache; determining if the D-cache line is unprefetchable; aging the D-cache line without a delay if the D-cache line is prefetchable; and aging the D-cache line with a delay if the D-cache line is unprefetchable.
Claims16
A method of providing history based done logic for a D-cache, the method comprising:
- receiving a D-cache line in an L2 cache;
- determining if the D-cache line is unprefetchable;
- aging the D-cache line without a delay if the D-cache line is prefetchable;
- and
- aging the D-cache line with a delay if the D-cache line is unprefetchable.
2 more elements
An integrated circuit device comprising:
- a processor core;
- a level one (L1) cache;
- a level two (L2) cache;
- and
- an aging count in the L1 cache for indicating a number of least recently used demotions to be skipped between actual demotions to a D-cache line in the L1 cache.
2 more elements
A processor device, comprising:
- a level one (L1) cache;
- a level two (L2) cache;
- circuitry configured to receive a D-cache line in the L2 cache, determine if the D-cache line is unprefetchable, age the D-cache line without a delay if the D-cache line is prefetchable;
- and age the D-cache line with a delay if the D-cache line is unprefetchable.
1 more element
Dependencies are inferred from the claim text.