Methods and Apparatus for Issuing Memory Barrier Commands in a Weakly Ordered Storage System

An apparatus for enforcing order of memory accesses, the apparatus comprising:

• a bus interface circuit that receives a memory access request from a device and communicates the memory access request to a memory hierarchy;
• and
• a surrogate barrier generator circuit which generates a surrogate barrier in response to the memory access request.

A method for coherency enforcement in a system, the method comprising:

• receiving a memory access request from a device through a bus interface which does not recognize memory barrier commands;
• and
• generating a surrogate barrier in response to the memory access request, wherein coherency is enforced within the system as if a memory barrier command was received from the device.

A method for enforcing order of memory accesses, the method comprising:

• receiving a memory read request from a device which is not configured to generate memory barrier commands;
• and
• enforcing order of memory accesses in response to the memory read request by withholding read data associated with the memory read request until previous memory access operations have been guaranteed to complete.