Memory Controllers
AssigneeVimicro Corporation
InventorChuan LIN
Life of this patent
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Abstract
Techniques pertaining the designs of memory controller are disclosed. According to one aspect of the present invention, a memory controller reduces delays in a data strobe signal of a DDR memory relative to a clock signal of a memory controller thereof. In one embodiment, the memory controller employs four IO ports, two inverters, six edge triggers and a multiplexer. By feeding back an inverted clock signal and utilizing the rising and filing edges of the clock signal, the delays in a data strobe signal of a DDR memory relative to a clock signal of a memory controller are considerably reduced or minimized.
Claims16
A memory controller comprising:
- a first sampling unit provided for sampling read data from a memory according to a data strobe from the memory;
- a second sampling unit provided for sampling the read data from the first sampling unit according to a first clock signal;
- a third sampling unit provided for sampling the read data from the first sampling unit according to a clock signal inverted with the first clock signal;
- a multiplexer provided for outputting one of read data from the second sampling unit and read data from the third sampling unit according to a selecting signal;
- a fourth sampling unit for sampling the first clock signal according to a second clock signal and providing the selecting signal;
- and
- a fifth sampling unit for sampling read data outputted from the multiplexer according to the second clock;
- wherein the first clock signal is provided from a clock terminal of the memory.
A memory controller comprising:
- a first sampling unit having an input terminal, an output terminal and a clock terminal coupled to a first clock signal;
- a second sampling unit having an input terminal coupled to the output terminal of the first sampling unit, an output terminal and a clock terminal coupled to the first clock signal;
- a third sampling unit having an input terminal coupled to the input terminal of the first sampling unit, an output terminal and a clock terminal coupled to a clock signal inverted with the first clock signal;
- a multiplexer having two input terminals coupled to the output terminal of the second sampling unit and the output terminal of the third sampling unit respectively, a control terminal and an output terminal;
- and
- a fourth sampling unit having an input terminal coupled to the first clock signal, an output terminal coupled to the control terminal and a clock terminal coupled to a second clock signal, wherein the first clock signal is inputted from a clock terminal of the memory and the second clock signal is an internal clock of the memory controller.
A memory controller comprising:
- a first sampling unit provided for sampling read data from a memory according to a data strobe from the memory;
- a second sampling unit provided for sampling read data outputted from the first sampling unit according to a first clock signal;
- a third sampling unit provided for sampling read data outputted from the first sampling unit according to a second clock signal;
- a multiplexer provided for outputting one of read data outputted from the second sampling unit and read data outputted from the third sampling unit according to a selecting signal;
- a fourth sampling unit for sampling the first clock signal according to a third clock signal and output the selecting signal;
- and
- a fifth sampling unit for sampling read data outputted from the multiplexer according to the third clock.
Dependencies are inferred from the claim text.