Memory device having integral instruction buffer
AssigneeNokia Corporation
InventorsEero T. Aho, Kimmo K. Kuusilinna, Jari A. Nikara
Life of this patent
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Abstract
A dynamic random access memory integrated circuit includes an interface to a serial interconnect, where the interface is configured to receive a plurality of memory access instructions over the serial interconnect, and a buffer configured to store the plurality of memory access instructions prior to execution of the buffered memory access instructions by the dynamic random access memory integrated circuit. The memory access instructions are received over at least one serial link that forms the serial interconnect, and the at least one serial link may be a shared bi-directional serial link or a uni-directional serial link.
Claims25
A method, comprising:
- receiving a plurality of memory access instructions over a serial interconnect at a dynamic random access memory integrated circuit;
- buffering the plurality of memory access instructions in the dynamic random access memory integrated circuit;
- and
- executing the buffered memory access instructions.
A dynamic random access memory integrated circuit, comprising:
- an interface to a serial interconnect, said interface configured to receive a plurality of memory access instructions over the serial interconnect;
- and
- a buffer configured to store the plurality of memory access instructions prior to execution of the buffered memory access instructions by the dynamic random access memory integrated circuit.
Dependencies are inferred from the claim text.