System and Method of Signal Processing Engines With Programmable Logic Fabric
AssigneeAgate Logic, Inc.
InventorsDana How, Godfrey P. D'Souza, Malcolm J. Wing, Colin N. Murphy, Arun Jangity
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Abstract
A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.
Claims42
A programmable integrated circuit having a bus structure for a cross-connection network for data (DCC network), comprising:
- a plurality of stations having an input station, one or more intermediate stations, and a destination station, each station comprising a pipeline register, the input station serializing data at a first frequency X, the one or more intermediate stations registering the serialized data at a second frequency Y, the destination station deserializing the data at a third frequency Z, the first frequency and the second frequency forming a first frequency ratio Y/X, the second frequency and the third frequency forming a second frequency ratio Y/Z;
- and
- connectors selectively joining each pipeline register at the corresponding station based on a select signal for selecting between special-purpose circuits, other pipeline registers, and logic circuits.
A programmable integrated circuit, comprising:
- a first station having a first serializer and a first pipeline register, the first serializer coupled to the first pipeline register, the first serializer having an input port for receiving input data at a first frequency and serializing the input data at a second frequency to generate serialized data at an output port;
- and
- a second station having a second pipeline register and a deserializer, the first pipeline register coupled to the second pipeline register, the second pipeline register coupled to the deserializer, the deserializer receiving the serialized data through the second pipeline register at the second frequency and deserializing the serialized data at a third frequency to generate an output data at an output port of the deserializer.
A method for data communication having a first station coupled a second station, the first station having a first serializer coupled to a first pipeline register, the second station having a second pipeline register coupled to a deserializer, comprising:
- serializing input data at a first frequency, by the first serializer, to serialized data at a second frequency;
- first registering the serialized data received from the serializer at the first pipeline register;
- second registering the serialized data received from the first pipeline register at the second pipeline register;
- and
- deserializing the serialized data at the second frequency from the second pipeline register to output data at a third frequency.
Dependencies are inferred from the claim text.